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1. 发明申请

US20230027064A1 Power Savings by Register Insertion in Large Combinational Circuits 有权
公开(公告)号：US20230027064A1
公开(公告)日：2023-01-26
申请号：US17957235
申请日：2022-09-30
申请人： Martin Langhammer , Gregg William Baeckler , Sergey Vladimirovich Gribok , Mahesh A. Iyer
发明人： Martin Langhammer , Gregg William Baeckler , Sergey Vladimirovich Gribok , Mahesh A. Iyer
IPC分类号： G06F1/06 , G06F1/3237 , H03K19/00
摘要： Systems and methods of the present disclosure provide techniques for reducing power consumption of a large combinational circuit using register insertion. In particular, a large circuit may be analyzed to determine the amount of signal switching at various logical points (e.g., stages in the computation) of the circuit. A clock sequence with many pulses in the period of a clock that runs the large combinatorial circuit may be generated. To balance the amount of signal switching at various logical points in the circuit, registers may be inserted at certain points in the large circuit with the clock pulses of the clock sequence assigned to the registers that may not have a constant frequency or may be phase shifted versions of the main clock.

2. 发明申请

US20190324724A1 Geometric Synthesis 审中-公开
公开(公告)号：US20190324724A1
公开(公告)日：2019-10-24
申请号：US16457094
申请日：2019-06-28
申请人： Sergey Vladimirovich Gribok , Gregg William Baeckler , Martin Langhammer
发明人： Sergey Vladimirovich Gribok , Gregg William Baeckler , Martin Langhammer
IPC分类号： G06F7/501 , G06F17/50 , G06F17/11
摘要： A computer-implemented method for programming an integrated circuit includes receiving a program design and determining one or more addition operations based on the program design. The method also includes performing geometric synthesis based on the one or more addition operations by determining a plurality of bits associated with the one or more addition operations and defining a plurality of counters that includes the plurality of bits. Furthermore, the method includes generating instructions configured to cause circuitry configured to perform the one or more addition operations to be implemented on the integrated circuit based on the plurality of counters. The circuitry includes first adder circuitry configured to add a portion of the plurality of bits and produce a carry-out value. The circuitry also includes second adder circuitry configured to determine a sum of a second portion of the plurality of bits and the carry-out value.

3. 发明申请

US20190318058A1 High Performance Regularized Network-on-Chip Architecture 审中-公开
公开(公告)号：US20190318058A1
公开(公告)日：2019-10-17
申请号：US16457114
申请日：2019-06-28
申请人： Gregg William Baeckler , Martin Langhammer , Sergey Vladimirovich Gribok
发明人： Gregg William Baeckler , Martin Langhammer , Sergey Vladimirovich Gribok
IPC分类号： G06F17/50
摘要： Techniques for designing and implementing networks-on-chip (NoCs) are provided. For example, a computer-implemented method for programming a network-on-chip (NoC) onto an integrated circuit includes determining a first portion of a plurality of registers to potentially be included in a NoC design, determining routing information regarding datapaths between registers of the first portion of the plurality of registers, and determining an expected performance associated with the first portion of the plurality of registers. The method also includes determining whether the expected performance is within a threshold range, including the first portion of the plurality of registers and the datapaths in the NoC design after determining that the expected performance is within the threshold range, and generating instructions configured to cause circuitry corresponding to the NoC design to be implemented on the integrated circuit.

4. 发明申请

US20210216318A1 Vector Processor Architectures 有权
公开(公告)号：US20210216318A1
公开(公告)日：2021-07-15
申请号：US17214646
申请日：2021-03-26
申请人： Martin Langhammer , Eriko Nurvitadhi , Gregg William Baeckler
发明人： Martin Langhammer , Eriko Nurvitadhi , Gregg William Baeckler
IPC分类号： G06F9/30 , G06F30/347 , G06F9/445
摘要： The present disclosure relates to an integrated circuit device that includes a plurality of vector registers configurable to store a plurality of vectors and switch circuitry communicatively coupled to the plurality of vector registers. The switch circuitry is configurable to route a portion of the plurality of vectors. Additionally, the integrated circuit device includes a plurality of vector processing units communicatively coupled to the switch circuitry. The plurality of vector processing units is configurable to receive the portion of the plurality of vectors, perform one or more operations involving the portion of the plurality of vector inputs, and output a second plurality of vectors generated by performing the one or more operations.

5. 发明授权

US09304899B1 Network interface circuitry with flexible memory addressing capabilities 有权
标题翻译：具有灵活存储器寻址能力的网络接口电路
公开(公告)号：US09304899B1
公开(公告)日：2016-04-05
申请号：US13594591
申请日：2012-08-24
申请人： Gregg William Baeckler
发明人： Gregg William Baeckler
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/023 , G06F13/128 , G06F13/16
摘要： An integrated circuit that includes network interface circuitry is provided. The network interface circuitry may include memory for buffering incoming data and associated control circuitry for loading the incoming data into and retrieving data from memory. The memory may be organized into multiple individually addressable memory blocks. The control circuitry may include read and write barrel shifters, a controller for providing read and write address signals, write address circuitry for controlling the write barrel shifter and for generating write address bits, and read address circuitry for controlling the read barrel shifter and for generating read address bits. The read and write circuitry may each include division and modulus arithmetic circuits for processing the address signals received from the controller and may include control logic for generating the read and write address bits that are used to address each of the multiple memory blocks.
摘要翻译：提供了包括网络接口电路的集成电路。网络接口电路可以包括用于缓冲输入数据的存储器和用于将输入数据加载到存储器中并从存储器检索数据的相关控制电路。存储器可以被组织成多个可单独寻址的存储器块。控制电路可以包括读取和写入桶形移位器，用于提供读取和写入地址信号的控制器，用于控制写入桶形移位器的写入地址电路和用于产生写入地址位，以及读取地址电路，用于控制读取桶形移位器并产生读地址位。读取和写入电路可以各自包括用于处理从控制器接收的地址信号的分割和模数运算电路，并且可以包括用于生成用于寻址多个存储器块中的每一个的读取和写入地址位的控制逻辑。

6. 发明授权

US08943393B1 Distributed burst error protection 有权
标题翻译：分布式突发错误保护
公开(公告)号：US08943393B1
公开(公告)日：2015-01-27
申请号：US13310628
申请日：2011-12-02
申请人： David W. Mendel , Gregg William Baeckler
发明人： David W. Mendel , Gregg William Baeckler
IPC分类号： G06F11/10
CPC分类号： H03M13/17 , G06F11/076 , H04L1/0072 , H04L2001/0096
摘要： A method of protecting digital words traversing multiple data paths is presented. The method identifies a number of bits for a header of a digital word and determines a number of protection bits for the header. A bit value for each of the protection bits is computed, and the computed bit values of the protection bits are transmitted through one or more data paths.
摘要翻译：提出了一种保护数字字遍历多个数据路径的方法。该方法识别数字字的头部的位数，并且确定头部的保护位数。计算每个保护位的位值，并且通过一个或多个数据路径发送保护位的计算位值。

7. 发明授权

US07877710B1 Method and apparatus for deriving signal activities for power analysis and optimization 有权
标题翻译：用于导出功率分析和优化的信号活动的方法和装置
公开(公告)号：US07877710B1
公开(公告)日：2011-01-25
申请号：US11414855
申请日：2006-05-01
申请人： David Neto , Vaughn Betz , Meghal Varia , Gregg William Baeckler
发明人： David Neto , Vaughn Betz , Meghal Varia , Gregg William Baeckler
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for managing vectorless estimation includes identifying a semantic structure. A signal activity is assigned to an output of the semantic structure. Vectorless estimation is performed on non-semantic structures.
摘要翻译：用于管理无向量估计的方法包括识别语义结构。信号活动被分配给语义结构的输出。对非语义结构进行无矢量估计。

8. 发明授权

US08166436B1 Early logic mapper during FPGA synthesis 有权
标题翻译： FPGA合成期间的早期逻辑映射器
公开(公告)号：US08166436B1
公开(公告)日：2012-04-24
申请号：US12430757
申请日：2009-04-27
申请人： Gregg William Baeckler
发明人： Gregg William Baeckler
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Programming software defining an algorithm that provides improved power, area and frequency predictability of a logic design early in the synthesis flow process, prior to Technology Mapping, without degrading the power, speed or area of the design implementation for PLDs. The method of the algorithm involves performing a high level synthesis of the logic design to generate a netlist, performing a multilevel synthesis on the netlist to generate a gate implementation of the netlist, and performing technology mapping on the gate implementation to map the gate implementation to actual resources on the target device. During the high level synthesis of the logic design into the netlist, technology mapping is performed on a selected portion of the logic design.
摘要翻译：编程软件定义了一种在技术映射之前在合成流程过程早期提供逻辑设计的功率，面积和频率可预测性的算法，而不会降低PLD设计实现的功率，速度或面积。该算法的方法涉及执行逻辑设计的高级合成以生成网表，在网表上执行多级综合以产生网表的门实现，以及在门实现上执行技术映射以将门实现映射到目标设备上的实际资源。在逻辑设计的高级合成到网表中，在逻辑设计的选定部分执行技术映射。

9. 发明授权

US07902864B1 Heterogeneous labs 有权
标题翻译：异质实验室
公开(公告)号：US07902864B1
公开(公告)日：2011-03-08
申请号：US11292856
申请日：2005-12-01
申请人： Michael D. Hutton , Keith Duwel , Gregg William Baeckler
发明人： Michael D. Hutton , Keith Duwel , Gregg William Baeckler
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： Disclosed is a programmable logic device (“PLD”) including at least one lookup table (“LUT”) based logic element (“LE”) of a first type and at least one LUT based LE of a second type. The first type of LE is different from the second type of LE. The term ‘different’ when used herein to describe the relationship of a first logic structure and/or its components to a second logic structure and/or its components indicates a difference in hardware design as opposed to a configuration difference or non-designed differences resulting, for example, from manufacturing variability. Additionally, a PLD can include at least one logic array block (“LAB”) of a first type having at least one LUT based LE and at least one LAB of a second type having at least one LUT based LE. The first type of LAB being different from the second type of LAB.
摘要翻译：公开了一种包括第一类型的至少一个查找表（“LUT”）逻辑元件（“LE”）和第二类型的至少一个基于LUT的LE的可编程逻辑器件（“PLD”）。 LE的第一种类型与第二种类型的LE不同。当用于描述第一逻辑结构和/或其组件与第二逻辑结构和/或其组件的关系时，术语“不同”表示硬件设计中的差异，而不是配置差异或非设计的差异，例如，从制造变异性。此外，PLD可以包括具有至少一个基于LUT的LE和具有至少一个基于LUT的LE的至少一个第二类型的至少一个LAB的第一类型的至少一个逻辑阵列块（“LAB”）。第一种类型的LAB与第二种类型的LAB不同。

10. 发明授权

US07634705B1 Methods and apparatus for error checking code decomposition 有权
标题翻译：错误检查代码分解的方法和装置
公开(公告)号：US07634705B1
公开(公告)日：2009-12-15
申请号：US11403342
申请日：2006-04-12
申请人： Gregg William Baeckler , Babette Van Antwerpen
发明人： Gregg William Baeckler , Babette Van Antwerpen
IPC分类号： H03M13/00
CPC分类号： H03M13/6575 , H03M13/091
摘要： Methods and apparatus are provided for more efficiently implementing error checking code circuitry on a programmable chip. In one example, Cyclic Redundancy Check (CRC) exclusive OR (XOR) circuitry is decomposed to allow efficient implementation on lookup tables (LUTs) of various sizes on a device. XOR cancellation factoring is used to break up wide CRC XORs into blocks that fit in various LUTs while maintaining focus on minimizing logic depth and logic area. Simulated annealing is used to further reduce logic area cost.
摘要翻译：提供了用于在可编程芯片上更有效地实现错误校验码电路的方法和装置。在一个示例中，循环冗余校验（CRC）异或（XOR）电路被分解以允许在设备上的各种尺寸的查找表（LUT）上的有效实现。 XOR取消因子分解用于将宽的CRC XOR分解成适合各种LUT的块，同时保持对最小化逻辑深度和逻辑区域的关注。模拟退火用于进一步降低逻辑面积成本。

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