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1. 发明申请

US20140286082A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20140286082A1
公开(公告)日：2014-09-25
申请号：US14018306
申请日：2013-09-04
申请人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
发明人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
摘要翻译：根据一个实施例，存储器件包括存储单元，读出放大器和电阻器。读出放大器包括第一输入和第二输入，根据第一和第二输入之间的差输出信号，并且在第二输入端选择性地耦合到存储单元。电阻器位于读出放大器的第一输入端和接地节点之间的第一路径中。

2. 发明申请

US20140286088A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20140286088A1
公开(公告)日：2014-09-25
申请号：US14018148
申请日：2013-09-04
申请人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
发明人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1659
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.
摘要翻译：根据一个实施例，存储器件包括存储器单元，读出放大器，单元结构和参考信号发生器。每个结构包括第一端，第一晶体管，第一局部线，可变电阻元件，第二晶体管，第二本地线和串联耦合的第三晶体管。参考信号发生器包括第一至第四全局线，以及第一和第二单元结构。第一单元结构在第一端耦合到第一全局线并且在第二端耦合到第三全局线。第二单元结构在第一端耦合到第四全局线并且在第二端耦合到第二全局线。

3. 发明申请

US20160019955A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20160019955A1
公开(公告)日：2016-01-21
申请号：US14872908
申请日：2015-10-01
申请人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
发明人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
摘要翻译：根据一个实施例，存储器件包括存储单元，读出放大器和电阻器。读出放大器包括第一输入和第二输入，根据第一和第二输入之间的差输出信号，并且在第二输入端选择性地耦合到存储单元。电阻器位于读出放大器的第一输入端和接地节点之间的第一路径中。

4. 发明申请

US20140286075A1 RESISTANCE CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20140286075A1
公开(公告)日：2014-09-25
申请号：US14018287
申请日：2013-09-04
申请人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
发明人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
IPC分类号： G11C13/00 , G11C5/08 , G11C5/06
CPC分类号： G11C13/004 , G11C5/06 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2013/0054
摘要： According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.
摘要翻译：根据一个实施例，存储器包括存储单元阵列，其包括沿列方向布置的块，第一和第二主全局导线，每列从列方向上从存储单元阵列的第一端延伸到第二端，第一电阻连接在存储单元阵列内部的第一和第二主要全局导电线之间的改变元件，从列方向上从存储单元阵列的第一端延伸到第二端的第一参考全局导电线，以及连接到存储单元阵列的第二电阻变化元件到存储单元阵列外的参考全局导线。

5. 发明申请

US20150070970A1 RESISTANCE CHANGE MEMORY AND TEST METHOD OF THE SAME 有权
标题翻译：电阻变化记忆及其测试方法
公开(公告)号：US20150070970A1
公开(公告)日：2015-03-12
申请号：US14201534
申请日：2014-03-07
申请人： Tsuneo INABA , Dong Keun KIM
发明人： Tsuneo INABA , Dong Keun KIM
IPC分类号： G11C29/12 , G11C13/00 , G11C11/16
CPC分类号： G11C29/12005 , G11C8/08 , G11C11/16 , G11C11/1675 , G11C13/0004 , G11C13/0069 , G11C29/06 , G11C29/50008 , G11C2013/009 , G11C2029/1202
摘要： According to one embodiment, a resistance change memory includes a memory cell array, an address counter, a word line driver, a power supply circuit, and a write driver. Memory cells include resistive storage elements and cell transistors. The power supply circuit generates a stress voltage different from a power supply voltage used to write data into the memory cells in a normal operation. The write driver applies the stress voltage across first bit and source lines to pass a stress current through the memory cell selected by a first word line. The write driver applies the stress voltage across second bit and source lines to pass the stress current through the memory cell selected by a second word line.
摘要翻译：根据一个实施例，电阻变化存储器包括存储单元阵列，地址计数器，字线驱动器，电源电路和写入驱动器。存储单元包括电阻存储元件和单元晶体管。电源电路产生与用于在正常操作中将数据写入存储单元的电源电压不同的应力电压。写驱动器将应力电压施加在第一位和源极线之间以将应力电流传递通过由第一字线选择的存储单元。写驱动器将应力电压施加在第二位和源极线之间，以使应力电流通过由第二字线选择的存储单元。

6. 发明申请

US20150340087A1 NONVOLATILE RANDOM ACCESS MEMORY 有权
标题翻译：非易失性随机存取存储器
公开(公告)号：US20150340087A1
公开(公告)日：2015-11-26
申请号：US14811237
申请日：2015-07-28
申请人： Masahiro TAKAHASHI , Dong Keun KIM , Hyuck Sang YIM
发明人： Masahiro TAKAHASHI , Dong Keun KIM , Hyuck Sang YIM
IPC分类号： G11C13/00 , G11C11/16
CPC分类号： G11C13/003 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054
摘要： According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.
摘要翻译：根据一个实施例，电阻变化存储器包括以下配置。第一反相器包括第一输入端和第一输出端以及第一和第二电压端。第二反相器包括第二输入端和第二输出端以及第三和第四电压端。第二输入端子连接到第一输出端子。第二输出端子连接到第一输入端子。第一和第二晶体管分别连接到第一和第二输出端子。第三和第四晶体管分别连接到第一和第三电压端子。第五晶体管连接在第一电压端和第一存储单元之间。第六晶体管连接到第三电压端子。在关闭第五和第六晶体管之后，控制器接通第一和第二晶体管。

7. 发明申请

US20140286081A1 RESISTANCE CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20140286081A1
公开(公告)日：2014-09-25
申请号：US14018242
申请日：2013-09-04
申请人： Masahiro TAKAHASHI , Akira KATAYAMA , Dong Keun KIM , Byoung Chan OH
发明人： Masahiro TAKAHASHI , Akira KATAYAMA , Dong Keun KIM , Byoung Chan OH
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C11/1693 , G11C13/00 , G11C13/0026 , G11C13/0061 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.
摘要翻译：根据一个实施例，电阻变化存储器包括存储单元，读出放大器和全局位线。存储单元设置在局部位线和字线相交的位置。存储单元连接到本地位线和字线。读出放大器通过向存储单元提供读取电流来读取存储在存储单元上的数据。全局位线连接在本地位线和读出放大器之间。全局位线将由读出放大器提供的读取电流馈送到本地位线。在本地位线和全局位线彼此连接之前，读出放大器对全局位线进行充电。

8. 发明申请

US20140286080A1 RESISTANCE CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20140286080A1
公开(公告)日：2014-09-25
申请号：US14018011
申请日：2013-09-04
申请人： Masahiro TAKAHASHI , Dong Keun KIM , Hyuck Sang YIM
发明人： Masahiro TAKAHASHI , Dong Keun KIM , Hyuck Sang YIM
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054
摘要： According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.
摘要翻译：根据一个实施例，电阻变化存储器包括以下配置。第一反相器包括第一输入端和第一输出端以及第一和第二电压端。第二反相器包括第二输入端和第二输出端以及第三和第四电压端。第二输入端子连接到第一输出端子。第二输出端子连接到第一输入端子。第一和第二晶体管分别连接到第一和第二输出端子。第三和第四晶体管分别连接到第一和第三电压端子。第五晶体管连接在第一电压端和第一存储单元之间。第六晶体管连接到第三电压端子。在关闭第五和第六晶体管之后，控制器接通第一和第二晶体管。

9. 发明申请

US20150179252A1 RESISTANCE CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20150179252A1
公开(公告)日：2015-06-25
申请号：US14636740
申请日：2015-03-03
申请人： Masahiro TAKAHASHI , Akira KATAYAMA , Dong Keun KIM , Byoung Chan OH
发明人： Masahiro TAKAHASHI , Akira KATAYAMA , Dong Keun KIM , Byoung Chan OH
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C11/1693 , G11C13/00 , G11C13/0026 , G11C13/0061 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.
摘要翻译：根据一个实施例，电阻变化存储器包括存储单元，读出放大器和全局位线。存储单元设置在局部位线和字线相交的位置。存储单元连接到本地位线和字线。读出放大器通过向存储单元提供读取电流来读取存储在存储单元上的数据。全局位线连接在本地位线和读出放大器之间。全局位线将由读出放大器提供的读取电流馈送到本地位线。在本地位线和全局位线彼此连接之前，读出放大器对全局位线进行充电。

10. 发明申请

US20120051127A1 SYSTEM FOR HANDLING DATA IN A SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：用于在半导体存储器中处理数据的系统
公开(公告)号：US20120051127A1
公开(公告)日：2012-03-01
申请号：US12982996
申请日：2010-12-31
申请人： Tae Hun YOON , Dong Keun KIM
发明人： Tae Hun YOON , Dong Keun KIM
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0071
摘要： A semiconductor memory apparatus includes a memory cell, a data transfer unit configured to adjust an access to the memory cell according to a voltage level of a selection signal, a selection signal output unit configured to output the selection signal having a first control voltage level in a data write mode and a second control voltage level in a data read mode. A data detection unit may also be configured to detect a voltage formed by a sensing current supplied to the memory cell through the data transfer unit in the data read mode, and output read data according to the detection result, wherein the second control voltage level is lower than the first control voltage level.
摘要翻译：一种半导体存储装置，包括存储单元，数据传送单元，被配置为根据选择信号的电压来调整对存储单元的访问;选择信号输出单元，被配置为输出具有第一控制电压电平的选择信号数据写入模式和第二控制电压电平。数据检测单元还可以被配置为在数据读取模式中检测通过数据传送单元提供给存储单元的感测电流形成的电压，并且根据检测结果输出读取数据，其中第二控制电压电平为低于第一控制电压电平。

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