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1. 发明申请

US20150294705A1 ELECTRONIC DEVICE 有权
标题翻译：电子设备
公开(公告)号：US20150294705A1
公开(公告)日：2015-10-15
申请号：US14563690
申请日：2014-12-08
申请人： Ji-Wang LEE , Dong-Keun KIM , Masahiro TAKAHASHI , Tsuneo INABA
发明人： Ji-Wang LEE , Dong-Keun KIM , Masahiro TAKAHASHI , Tsuneo INABA
IPC分类号： G11C11/16 , G11C13/00
CPC分类号： G11C11/1673 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/5607 , G11C11/5657 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C16/28 , G11C2013/0054 , G11C2213/79
摘要： A semiconductor memory unit includes first to Nth variable resistance elements each having different resistance values according to values stored therein, wherein N is a natural number equal to or greater than 2; a reference resistance element having a first reference resistance value; and first to Nth comparison units which correspond to the first to Nth variable resistance elements, respectively, and each of which determines whether a resistance value of the corresponding variable resistance element is greater or less than a second reference resistance value, wherein the first to Nth comparison units are commonly coupled to the reference resistance element.
摘要翻译：半导体存储单元包括根据存储在其中的值具有不同电阻值的第一至第N可变电阻元件，其中N是等于或大于2的自然数; 具有第一参考电阻值的参考电阻元件; 以及分别对应于第一至第N可变电阻元件的第一至第N比较单元，并且每个比较单元确定相应的可变电阻元件的电阻值是否大于或小于第二参考电阻值，其中第一至第N 比较单元通常耦合到参考电阻元件。

2. 发明申请

US20140286088A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20140286088A1
公开(公告)日：2014-09-25
申请号：US14018148
申请日：2013-09-04
申请人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
发明人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1659
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.
摘要翻译：根据一个实施例，存储器件包括存储器单元，读出放大器，单元结构和参考信号发生器。每个结构包括第一端，第一晶体管，第一局部线，可变电阻元件，第二晶体管，第二本地线和串联耦合的第三晶体管。参考信号发生器包括第一至第四全局线，以及第一和第二单元结构。第一单元结构在第一端耦合到第一全局线并且在第二端耦合到第三全局线。第二单元结构在第一端耦合到第四全局线并且在第二端耦合到第二全局线。

3. 发明申请

US20140286082A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20140286082A1
公开(公告)日：2014-09-25
申请号：US14018306
申请日：2013-09-04
申请人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
发明人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
摘要翻译：根据一个实施例，存储器件包括存储单元，读出放大器和电阻器。读出放大器包括第一输入和第二输入，根据第一和第二输入之间的差输出信号，并且在第二输入端选择性地耦合到存储单元。电阻器位于读出放大器的第一输入端和接地节点之间的第一路径中。

4. 发明申请

US20160019955A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20160019955A1
公开(公告)日：2016-01-21
申请号：US14872908
申请日：2015-10-01
申请人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
发明人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
摘要翻译：根据一个实施例，存储器件包括存储单元，读出放大器和电阻器。读出放大器包括第一输入和第二输入，根据第一和第二输入之间的差输出信号，并且在第二输入端选择性地耦合到存储单元。电阻器位于读出放大器的第一输入端和接地节点之间的第一路径中。

5. 发明申请

US20140286075A1 RESISTANCE CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20140286075A1
公开(公告)日：2014-09-25
申请号：US14018287
申请日：2013-09-04
申请人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
发明人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
IPC分类号： G11C13/00 , G11C5/08 , G11C5/06
CPC分类号： G11C13/004 , G11C5/06 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2013/0054
摘要： According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.
摘要翻译：根据一个实施例，存储器包括存储单元阵列，其包括沿列方向布置的块，第一和第二主全局导线，每列从列方向上从存储单元阵列的第一端延伸到第二端，第一电阻连接在存储单元阵列内部的第一和第二主要全局导电线之间的改变元件，从列方向上从存储单元阵列的第一端延伸到第二端的第一参考全局导电线，以及连接到存储单元阵列的第二电阻变化元件到存储单元阵列外的参考全局导线。

6. 发明申请

US20150332760A1 ELECTRONIC DEVICE 有权
标题翻译：电子设备
公开(公告)号：US20150332760A1
公开(公告)日：2015-11-19
申请号：US14563645
申请日：2014-12-08
申请人： Dong-Keun KIM , Masahiro TAKAHASHI , Tsuneo INABA
发明人： Dong-Keun KIM , Masahiro TAKAHASHI , Tsuneo INABA
IPC分类号： G11C13/00 , G06F12/08
CPC分类号： G11C13/004 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F12/0207 , G06F12/08 , G06F12/0875 , G06F2212/2024 , G06F2212/452 , G06F2212/60 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/4099 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C2013/0054 , G11C2213/79 , G11C2213/82
摘要： Disclosed is an electronic device including a semiconductor device, wherein the semiconductor device includes: a word line driving unit; a first cell array arranged at one side of the word line driving unit; a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit; and a read control unit.
摘要翻译：公开了一种包括半导体器件的电子器件，其中半导体器件包括：字线驱动单元; 布置在字线驱动单元的一侧的第一单元阵列; 布置在所述字线驱动单元的另一侧的第二单元阵列; 偏置电压产生单元; 和读取控制单元。

7. 发明申请

US20150070970A1 RESISTANCE CHANGE MEMORY AND TEST METHOD OF THE SAME 有权
标题翻译：电阻变化记忆及其测试方法
公开(公告)号：US20150070970A1
公开(公告)日：2015-03-12
申请号：US14201534
申请日：2014-03-07
申请人： Tsuneo INABA , Dong Keun KIM
发明人： Tsuneo INABA , Dong Keun KIM
IPC分类号： G11C29/12 , G11C13/00 , G11C11/16
CPC分类号： G11C29/12005 , G11C8/08 , G11C11/16 , G11C11/1675 , G11C13/0004 , G11C13/0069 , G11C29/06 , G11C29/50008 , G11C2013/009 , G11C2029/1202
摘要： According to one embodiment, a resistance change memory includes a memory cell array, an address counter, a word line driver, a power supply circuit, and a write driver. Memory cells include resistive storage elements and cell transistors. The power supply circuit generates a stress voltage different from a power supply voltage used to write data into the memory cells in a normal operation. The write driver applies the stress voltage across first bit and source lines to pass a stress current through the memory cell selected by a first word line. The write driver applies the stress voltage across second bit and source lines to pass the stress current through the memory cell selected by a second word line.
摘要翻译：根据一个实施例，电阻变化存储器包括存储单元阵列，地址计数器，字线驱动器，电源电路和写入驱动器。存储单元包括电阻存储元件和单元晶体管。电源电路产生与用于在正常操作中将数据写入存储单元的电源电压不同的应力电压。写驱动器将应力电压施加在第一位和源极线之间以将应力电流传递通过由第一字线选择的存储单元。写驱动器将应力电压施加在第二位和源极线之间，以使应力电流通过由第二字线选择的存储单元。

8. 发明申请

US20100103718A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100103718A1
公开(公告)日：2010-04-29
申请号：US12559335
申请日：2009-09-14
申请人： Yoshiaki ASAO , Takeshi KAJIYAMA , Tsuneo INABA
发明人： Yoshiaki ASAO , Takeshi KAJIYAMA , Tsuneo INABA
IPC分类号： G11C11/00 , G11C5/06 , G11C11/14
CPC分类号： G11C11/1659
摘要： A semiconductor memory device includes first and second bit line provided in the same level layer above a semiconductor substrate, a first variable-resistance element disposed under the first bit line, having one terminal connected to one end of a current path of a first MOSFET, a second variable-resistance element disposed under the second bit line, and having one terminal connected to one end of a current path of a second MOSFET, a first interconnect layer connecting the first bit line to the other terminal of the first variable-resistance element, and connecting the first bit line to the other end of the current path of the second MOSFET, and a second interconnect layer connecting the second bit line to the other terminal of the second variable-resistance element, and connecting the second bit line to the other end of the current path of the first MOSFET.
摘要翻译：半导体存储器件包括设置在半导体衬底上的同一电平层中的第一和第二位线，设置在第一位线下方的第一可变电阻元件，其一端连接到第一MOSFET的电流通路的一端，第二可变电阻元件，设置在第二位线下方，并且具有连接到第二MOSFET的电流通路的一端的一个端子，将第一位线连接到第一可变电阻元件的另一端子的第一互连层并且将第一位线连接到第二MOSFET的电流路径的另一端，以及将第二位线连接到第二可变电阻元件的另一端的第二互连层，并将第二位线连接到第二位线第一个MOSFET的电流通路的另一端。

9. 发明申请

US20100008125A1 SEMICONDUCTOR MEMORY DEVICE AND REDUNDANCY METHOD THEREFOR 有权
标题翻译：半导体存储器件及其冗余方法
公开(公告)号：US20100008125A1
公开(公告)日：2010-01-14
申请号：US12414083
申请日：2009-03-30
申请人： Tsuneo INABA
发明人： Tsuneo INABA
IPC分类号： G11C11/00 , G11C29/00
CPC分类号： G11C5/02 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C29/025 , G11C2213/71 , G11C2213/72
摘要： A memory cell array is formed by arranging memory cells at intersections of plural first wirings and plural second wirings, and a rectifying element and a variable resistive element are connected in series in the memory cell. The variable resistive element has at least a first resistance value and a second resistance value that is higher than the first resistance value. The control circuit selectively drives the first wirings and the second wirings. The control circuit can perform a short-circuit failure countermeasure program operation. In the short-circuit failure countermeasure program operation, the variable resistive element of the memory cell whose rectifying element is in a short-circuit failure state is programmed from the first resistance value to the second resistance value.
摘要翻译：存储单元阵列通过在多个第一布线和多个第二布线的交叉处布置存储单元而形成，并且整流元件和可变电阻元件串联连接在存储单元中。可变电阻元件具有比第一电阻值高的至少第一电阻值和第二电阻值。控制电路选择性地驱动第一布线和第二布线。控制电路可以执行短路故障对策程序操作。在短路故障对策编程动作中，将整流元件处于短路故障状态的存储单元的可变电阻元件从第一电阻值编程为第二电阻值。

10. 发明申请

US20110069534A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110069534A1
公开(公告)日：2011-03-24
申请号：US12883019
申请日：2010-09-15
申请人： Tsuneo INABA
发明人： Tsuneo INABA
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C7/18 , G11C11/1657 , G11C11/1659 , Y10S977/935
摘要： According to one embodiment, a semiconductor memory device includes bit line pairs extending in a column direction, each of the bit line pairs includes a first bit line and a second bit line, and memory cell groups connected to the bit line pairs, respectively, and each includes memory cells. Each of the memory cells comprises a first transistor, a second transistor and a resistive memory element. One end of the resistive memory element is connected to the first bit line. A drain region of the first transistor and a drain region of the second transistor are connected to each other and connected to the other end of the resistive memory element. A source region of the first transistor and a source region of the second transistor are connected to the second bit line.
摘要翻译：根据一个实施例，半导体存储器件包括沿列方向延伸的位线对，每个位线对包括第一位线和第二位线，以及分别连接到位线对的存储单元组，以及每个都包含存储单元。每个存储单元包括第一晶体管，第二晶体管和电阻存储元件。电阻性存储元件的一端连接到第一位线。第一晶体管的漏极区域和第二晶体管的漏极区域彼此连接并连接到电阻存储元件的另一端。第一晶体管的源极区域和第二晶体管的源极区域连接到第二位线。

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