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1. 发明申请

US20070198114A1 Three-dimensional device simulation program product and three-dimensional device simulation system 有权
标题翻译：三维设备仿真程序产品和三维设备仿真系统
公开(公告)号：US20070198114A1
公开(公告)日：2007-08-23
申请号：US11443200
申请日：2006-05-31
申请人： Masayoshi Hashima , Yuichi Sato , Shuji Takeshita
发明人： Masayoshi Hashima , Yuichi Sato , Shuji Takeshita
IPC分类号： G06F19/00
CPC分类号： G05B19/4068 , G05B2219/35318 , G05B2219/45031
摘要： A computer executable three-dimensional device simulation program product for the purpose of making a three-dimensional device simulation system which generates a three-dimensional model of a device by using a mask data performing the procedures of inputting cross-sectional feature information indicating a cross-sectional feature of an edge part of a mask, and calculating the three-dimensional model based on the mask data and input cross-sectional feature information, thereby enabling an easy generation of a complex three-dimensional feature by using pattern forming-use mask data when generating a three-dimensional feature model of a minute device.
摘要翻译：一种用于制造三维装置模拟系统的计算机可执行三维装置模拟程序产品，该系统通过使用执行输入横截面特征信息的程序的掩模数据来产生装置的三维模型掩模的边缘部分的截面特征，并且基于掩模数据和输入横截面特征信息计算三维模型，由此通过使用图案形成用掩模来简化生成复杂的三维特征生成分钟装置的三维特征模型时的数据。

2. 发明授权

US07958462B2 Computer-readable non-transitory medium storing three-dimensional device simulation program and three-dimensional device simulation system 有权
标题翻译：计算机可读的非瞬态介质，存储三维设备仿真程序和三维设备仿真系统
公开(公告)号：US07958462B2
公开(公告)日：2011-06-07
申请号：US11443200
申请日：2006-05-31
申请人： Masayoshi Hashima , Yuichi Sato , Shuji Takeshita
发明人： Masayoshi Hashima , Yuichi Sato , Shuji Takeshita
IPC分类号： G06F17/50
CPC分类号： G05B19/4068 , G05B2219/35318 , G05B2219/45031
摘要： A computer executable three-dimensional device simulation program product for the purpose of making a three-dimensional device simulation system which generates a three-dimensional model of a device by using a mask data performing the procedures of inputting cross-sectional feature information indicating a cross-sectional feature of an edge part of a mask, and calculating the three-dimensional model based on the mask data and input cross-sectional feature information, thereby enabling an easy generation of a complex three-dimensional feature by using pattern forming-use mask data when generating a three-dimensional feature model of a minute device.
摘要翻译：一种计算机可执行三维设备仿真程序产品，用于制造三维设备仿真系统，其通过使用执行输入指示交叉的横截面特征信息的过程的掩码数据来生成设备的三维模型掩模的边缘部分的截面特征，并且基于掩模数据和输入横截面特征信息来计算三维模型，从而通过使用图案形成用掩模来容易地生成复杂的三维特征生成分钟装置的三维特征模型时的数据。

3. 发明授权

US6110568A Thin film circuit substrate and process for the manufacture thereof 失效
标题翻译：薄膜电路基板及其制造方法
公开(公告)号：US6110568A
公开(公告)日：2000-08-29
申请号：US302085
申请日：1994-09-07
申请人： Shuji Takeshita
发明人： Shuji Takeshita
IPC分类号： H05K3/38 , H01L23/14 , H01L23/498 , H01L23/538 , H05K1/02 , H05K3/00 , H05K3/46 , B32B3/00
CPC分类号： H05K1/024 , H01L23/145 , H01L23/49894 , H01L23/538 , H01L23/5384 , H01L2924/0002 , H05K2201/0187 , H05K2201/0195 , H05K2201/0715 , H05K2203/1184 , H05K3/0041 , Y10S428/901 , Y10T428/24917
摘要： A thin film circuit substrate comprising multilayer conductor layers formed via insulating layers, wherein a signal transmission path in at least one of the conductor layers is embedded in a low dielectric constant insulator, and the low dielectric constant insulator is embedded in an insulator layer with a good adhesiveness. The thin film circuit substrate attains a low dielectric constant, and thus an improved signal propagation velocity, without lowering the interlayer adhesiveness.
摘要翻译： 1.一种薄膜电路基板，包括通过绝缘层形成的多层导体层，其中至少一个所述导体层中的信号传输路径嵌入在低介电常数绝缘体中，并且所述低介电常数绝缘体嵌入绝缘体层中，所述绝缘体层具有粘合性好薄膜电路基板获得低的介电常数，从而提高信号传播速度，而不降低层间粘合性。

4. 发明授权

US5362550A Thin film circuit board and its manufacturing process 失效
标题翻译：薄膜电路板及其制造工艺
公开(公告)号：US5362550A
公开(公告)日：1994-11-08
申请号：US19565
申请日：1993-02-18
申请人： Shuji Takeshita
发明人： Shuji Takeshita
IPC分类号： H01L21/48 , H01L23/64 , H01L23/66 , H05K1/00 , H05K1/02 , H05K1/03 , H05K3/00 , H05K3/28 , H05K3/46 , B32B9/00
CPC分类号： H01L23/66 , H01L21/4846 , H01L23/642 , H05K1/024 , H05K3/002 , H05K3/28 , H01L2924/0002 , H05K1/036 , H05K2201/0154 , H05K2201/0187 , H05K2201/0317 , H05K2203/1184 , H05K3/4676 , Y10T428/24917
摘要： A thin film circuit board has an insulator layer and a conductor layer embedded in the insulator layer and supported in an undercut state by an insulator. The entire conductor layer, excluding the portion supported by the insulator, is surrounded by an insulator having a relatively low dielectric constant which in turn is surrounded by an insulator having a relatively high dielectric constant. The insulator portion that supports the conductor layer in the undercut state has a relatively high etching rate and is formed in a desired thickness on an insulator layer having a relatively low etching rate.
摘要翻译：薄膜电路板具有绝缘体层和嵌入在绝缘体层中并由绝缘体以底切状态支撑的导体层。不包括由绝缘体支撑的部分的整个导体层被具有相对较低介电常数的绝缘体包围，绝缘体又由具有相对较高介电常数的绝缘体围绕。支撑处于底切状态的导体层的绝缘体部分具有相对较高的蚀刻速率，并且在具有较低蚀刻速率的绝缘体层上形成所需厚度。

5. 发明授权

US5928838A Process for manufacturing a printed circuit board using a mask with gradual increase in transmittance from opaque to transparent region 失效
标题翻译：使用掩模制造印刷电路板的方法，其透光率从不透明区域逐渐增加到透明区域
公开(公告)号：US5928838A
公开(公告)日：1999-07-27
申请号：US968479
申请日：1997-11-12
申请人： Shuji Takeshita
发明人： Shuji Takeshita
IPC分类号： G03F1/68 , G03F1/00 , H05K3/00 , H05K3/46 , G03F7/20
CPC分类号： H05K3/0002 , G03F1/50 , H05K2203/056 , H05K3/0082 , H05K3/4644
摘要： A method of exposing a photoresist layer deposited on a substrate uses an exposure mask having transparent and opaque regions defined on a mask substrate and a transition region defined on said mask substrate between said transparent region and said opaque region. The transition region comprises a plurality of opaque patterns having respective sizes and disposed with respective mutual separations such that said transmission region has a gradually increasing transmittance proceeding from said opaque region to said transparent region. The exposed photoresist layer is developed to form a resist pattern and the resist pattern is converted into an insulation pattern by conducting a baking process.
摘要翻译：曝光沉积在基板上的光致抗蚀剂层的方法使用曝光掩模，其具有限定在掩模基板上的透明和不透明区域以及在所述透明区域和所述不透明区域之间限定在所述掩模基板上的过渡区域。过渡区域包括具有各自尺寸的多个不透明图案，并且设置有相应的相互间隔，使得所述透射区域具有从所述不透明区域到所述透明区域的逐渐增加的透射率。曝光的光致抗蚀剂层被显影以形成抗蚀剂图案，并且通过进行烘焙处理将抗蚀剂图案转变成绝缘图案。

6. 发明授权

US5298114A Thin film circuit substrate and process for the manufacture thereof 失效
标题翻译：薄膜电路基板及其制造方法
公开(公告)号：US5298114A
公开(公告)日：1994-03-29
申请号：US38272
申请日：1993-03-29
申请人： Shuji Takeshita
发明人： Shuji Takeshita
IPC分类号： H05K3/38 , H01L23/14 , H01L23/498 , H01L23/538 , H05K1/02 , H05K3/00 , H05K3/46 , B44C1/22 , B29C37/00 , C23F1/00
CPC分类号： H05K1/024 , H01L23/145 , H01L23/49894 , H01L23/538 , H01L23/5384 , H01L2924/0002 , H05K2201/0187 , H05K2201/0195 , H05K2201/0715 , H05K2203/1184 , H05K3/0041 , Y10S428/901 , Y10T428/24917 , Y10T428/31681
摘要： A thin film circuit substrate comprising multilayer conductor layers formed via insulating layers, wherein a signal transmission path in at least one of the conductor layers is embedded in a low dielectric constant insulator, and the low dielectric constant insulator is embedded in an insulator layer with a good adhesiveness. The thin film circuit substrate attains a low dielectric constant, and thus an improved signal propagation velocity, without lowering the interlayer adhesiveness.
摘要翻译： 1.一种薄膜电路基板，包括通过绝缘层形成的多层导体层，其中至少一个所述导体层中的信号传输路径嵌入在低介电常数绝缘体中，并且所述低介电常数绝缘体嵌入绝缘体层中，所述绝缘体层具有粘合性好薄膜电路基板获得低的介电常数，从而提高信号传播速度，而不降低层间粘合性。

7. 发明授权

US5417800A Thin film circuit board manufacturing process 失效
标题翻译：薄膜电路板制造工艺
公开(公告)号：US5417800A
公开(公告)日：1995-05-23
申请号：US264308
申请日：1994-06-23
申请人： Shuji Takeshita
发明人： Shuji Takeshita
IPC分类号： H01L21/48 , H01L23/64 , H01L23/66 , H05K1/00 , H05K1/02 , H05K1/03 , H05K3/00 , H05K3/28 , H05K3/46 , B44C1/22 , B29C37/00 , C03C15/00
CPC分类号： H01L23/66 , H01L21/4846 , H01L23/642 , H05K1/024 , H05K3/002 , H05K3/28 , H01L2924/0002 , H05K1/036 , H05K2201/0154 , H05K2201/0187 , H05K2201/0317 , H05K2203/1184 , H05K3/4676 , Y10T428/24917
摘要： A process for manufacturing a thin film circuit board includes forming an insulator layer having a relatively high etching rate in a desired thickness on an insulator layer having a relatively low etching rate and a relatively high dielectric constant, arranging a conductor layer on the insulator layer having a relatively high etching rate, selectively removing the insulator having a relatively high etching rate by etching but excluding a portion located beneath the conductor layer, forming an insulator portion that contains the insulator layer having a relatively high etching rate and supports the conductor layer in the undercut state, forming an insulator layer having a relatively low dielectric constant so as to surround the entire conductor layer, and forming an insulator layer having a relatively high dielectric constant on top of the insulator layer having a relatively low dielectric constant so as to surround the entire insulator layer having a relatively low dielectric constant.
摘要翻译：一种制造薄膜电路板的方法包括在具有相对低的蚀刻速率和相对高的介电常数的绝缘体层上形成具有希望厚度的较高蚀刻速率的绝缘体层，在具有相对高的蚀刻速率，通过蚀刻选择性地去除具有相对高的蚀刻速率的绝缘体，但不包括位于导体层下方的部分，形成绝缘体部分，其包含具有相对高的蚀刻速率的绝缘体层并且将导体层支撑在形成具有相对较低介电常数的绝缘体层，以便围绕整个导体层，并且在具有相对低介电常数的绝缘体层的顶部上形成具有较高介电常数的绝缘体层，以便围绕整个绝缘体层具有相对低的介电常数。

8. 发明申请

US20130014639A1 DIAPHRAGM 审中-公开
公开(公告)号：US20130014639A1
公开(公告)日：2013-01-17
申请号：US13637877
申请日：2011-03-24
申请人： Shuji Takeshita , Kazuma Shigeta , Koji Aoba
发明人： Shuji Takeshita , Kazuma Shigeta , Koji Aoba
IPC分类号： F01B19/02
CPC分类号： F16J3/02 , F15B1/125 , F15B2201/205 , F15B2201/3151 , F15B2201/3156 , F15B2201/61
摘要： Disclosed is a diaphragm having a flexible film portion and an outer peripheral flange portion integrally provided on the peripheral edge of the film portion, said outer peripheral flange portion being provided between and held by a first housing and a second housing, wherein the film portion is prevented from rising upward when the diaphragm is attached to the housings. The outer peripheral flange portion has a first pressed surface which is one surface of the diaphragm in the thickness direction and which is in close contact with the first housing, and a three-dimensional shape composed of a projected portion or a recessed portion, on the first pressed surface. When the outer peripheral flange portion is attached to the first housing and the second housing while being compressed and deformed therebetween, the three-dimensional shape defines voids in the thickness direction between the outer peripheral flange portion and the first housing.
摘要翻译：公开了一种膜片，其具有柔性膜部分和一体地设置在膜部分的周缘上的外周边凸缘部分，所述外周凸缘部分设置在第一壳体和第二壳体之间并由第一壳体和第二壳体保持，其中膜部分当隔膜附接到壳体时，防止其向上升起。外周凸缘部分具有第一挤压表面，该第一压制表面是厚度方向上的膜片的一个表面，并且与第一壳体紧密接触，并且具有由突出部分或凹入部分组成的三维形状第一次按压表面。当外周凸缘部分在第一壳体和第二壳体之间被压缩和变形地附接到第二壳体和第二壳体时，三维形状在外周凸缘部分和第一壳体之间限定厚度方向上的空隙。

9. 发明授权

US5725972A Mask with gradual increase in transmittance from opaque to transparent region 失效
标题翻译：面罩从不透明区域到透明区域的透光率逐渐增加
公开(公告)号：US5725972A
公开(公告)日：1998-03-10
申请号：US612163
申请日：1996-03-07
申请人： Shuji Takeshita
发明人： Shuji Takeshita
IPC分类号： G03F1/68 , G03F1/00 , H05K3/00 , H05K3/46 , G03F9/00
CPC分类号： H05K3/0002 , G03F1/50 , H05K2203/056 , H05K3/0082 , H05K3/4644
摘要： An exposure mask includes a transparent region and an opaque region defined on a transparent substrate, with a transition region formed between he transparent region and the opaque region by a plurality of opaque patterns disposed with respective sizes and respective mutual separations changed gradually and continuously from the opaque region toward the transparent region, such that exposure dose increases gradually and consecutively from the opaque region toward the transparent region.
摘要翻译：曝光掩模包括透明区域和限定在透明基板上的不透明区域，其中透明区域和不透明区域之间形成的过渡区域通过多个不透明图案形成，所述多个不透明图案以相应尺寸和相应的相互间隔逐渐且连续地从不透明区域朝向透明区域，使得曝光剂量从不透明区域朝向透明区域逐渐且连续地增加。

10. 发明授权

US4851903A Automatic focusing system of an observing means for inspecting an object 失效
标题翻译：用于检查物体的观察装置的自动对焦系统
公开(公告)号：US4851903A
公开(公告)日：1989-07-25
申请号：US105734
申请日：1987-10-07
申请人： Hiroshi Ikeda , Shuji Takeshita
发明人： Hiroshi Ikeda , Shuji Takeshita
IPC分类号： G01B11/24 , G01N21/88 , G01N21/93 , G01N21/956 , G02B7/28 , H04N5/232 , H05K3/00
CPC分类号： H04N5/23212
摘要： A TV camera for visually inspecting an object is focused to a designated inspecting point, while being shifted to that inspecting point by utilizing a calculated distance from the TV camera to the next inspecting point without actually measuring the distance. The distance to the next inspecting point is calculated from a plane equation several of triangular planes formed over the object by a plurality of reference points previously designated on the object. The plane equations are calculated before executing inspection, by using distances, actually measured by distance measuring means, from the TV camera to the reference points.
摘要翻译：用于目视检查物体的电视摄像机被聚焦到指定的检查点，同时通过利用从电视摄像机到下一个检查点的计算距离而移动到该检查点，而不实际测量距离。距离下一个检查点的距离是从多个先前在物体上指定的参考点在物体上形成的几个三角形平面的平面等式计算的。通过使用由距离测量装置实际测量的距离，从TV摄像机到参考点，在执行检查之前计算平面方程。

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