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1. 发明授权

US10076044B2 Method for manufacturing multilayer wiring substrate 有权
公开(公告)号：US10076044B2
公开(公告)日：2018-09-11
申请号：US15027756
申请日：2014-09-24
申请人： HITACHI CHEMICAL COMPANY, LTD.
发明人： Nobuyuki Yoshida
IPC分类号： H05K3/42 , H05K3/00 , H05K3/46
CPC分类号： H05K3/423 , H05K3/0026 , H05K3/0035 , H05K3/421 , H05K3/4652 , H05K2201/0355 , H05K2201/09863 , H05K2201/2072 , H05K2203/1184 , H05K2203/1476 , H05K2203/1492
摘要： The present invention is a method for manufacturing a multilayer wiring board having (1) a step of providing with a hole for a via hole from a metal foil for an upper layer wiring pattern to an inner layer wiring pattern by using a conformal method or a direct laser method, and (2) a step of forming a via hole by forming electrolytic filling plating layers in the hole for a via hole, wherein the formation of the electrolytic filling plating layers in the step (2) is carried out by repeating change in electric current density of temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating and then increasing it again, two or more times before the electrolytic filling plating layers block an opening of the hole for a via hole.

2. 发明申请

US20170055347A1 Printed Circuit Board And Method Of Manufacturing The Same 有权
标题翻译：印刷电路板及其制造方法
公开(公告)号：US20170055347A1
公开(公告)日：2017-02-23
申请号：US15241714
申请日：2016-08-19
申请人： LG INNOTEK CO., LTD.
发明人： Jung Ho Hwang , Han Su Lee , Dae Young Choi , Soon Gyu Kwon , Dong Hun Jeong , In Ho Jeong , Kil Dong Son , Sang Hwa Kim , Sang Young Lee , Jae Hoon Jeon , Jin Hak Lee , Yun Mi Bae
IPC分类号： H05K1/02 , H05K1/09
CPC分类号： H05K3/188 , H05K1/0298 , H05K1/09 , H05K3/002 , H05K3/108 , H05K3/244 , H05K2201/0347 , H05K2201/098 , H05K2203/0548 , H05K2203/0588 , H05K2203/0723 , H05K2203/1184
摘要： Disclosed are a printed circuit board and a method of manufacturing the printed circuit board. The printed circuit board includes an insulating layer, and a circuit pattern formed on the insulating layer, wherein the circuit pattern includes a first circuit pattern formed on the insulating layer and including a corner portion of an upper portion which has a predetermined curvature and a second circuit pattern formed on the first circuit pattern and configured to cover an upper surface of the first circuit pattern including the corner portion.
摘要翻译：公开了印刷电路板和制造印刷电路板的方法。印刷电路板包括绝缘层和形成在绝缘层上的电路图案，其中电路图案包括形成在绝缘层上并包括具有预定曲率的上部的角部的第一电路图案，电路图案形成在第一电路图案上并且被配置为覆盖包括拐角部分的第一电路图案的上表面。

3. 发明申请

US20160242285A1 PRINTED WIRING BOARD 有权
标题翻译：印刷线路板
公开(公告)号：US20160242285A1
公开(公告)日：2016-08-18
申请号：US15044380
申请日：2016-02-16
申请人： IBIDEN CO., LTD.
发明人： Takayuki Katsuno , Yuki Ito , Takeshi Furusawa , Takema Adachi
IPC分类号： H05K1/11 , H05K1/09
CPC分类号： H05K1/0271 , H05K3/007 , H05K3/025 , H05K3/188 , H05K3/244 , H05K2201/0338 , H05K2201/0344 , H05K2201/098 , H05K2203/1184
摘要： A printed wiring board includes a resin insulating layer having recess portions formed on first surface, a first conductor layer formed in the recess portions and including pads positioned to mount an electronic component, conductive pillars formed on the pads, respectively, and formed to mount the electronic component onto the resin insulating layer, a second conductor layer formed on second surface of the resin insulating layer on the opposite side with respect to the first surface, and a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer and connecting the first and second conductor layers. The pillars is formed such that each of the pads has an exposed surface exposed from a respective one of the conductive pillars, and the pads are formed such that the exposed surface is recessed from the first surface of the resin insulating layer.
摘要翻译：印刷电路板包括具有形成在第一表面上的凹部的树脂绝缘层，形成在凹部中的第一导体层，并且包括分别安装电子部件的焊盘，形成在焊盘上的导电柱，并形成为安装电子部件到树脂绝缘层上，在相对于第一表面的相对侧的树脂绝缘层的第二表面上形成的第二导体层和形成在树脂绝缘层中的通孔导体，使得通孔导体穿透树脂绝缘层并连接第一和第二导体层。柱形成为使得每个焊盘具有从相应的一个导电柱露出的暴露表面，并且焊盘被形成为使得暴露的表面从树脂绝缘层的第一表面凹陷。

4. 发明申请

US20160192482A1 PATTERNED CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：图形导电结构及其形成方法
公开(公告)号：US20160192482A1
公开(公告)日：2016-06-30
申请号：US14583446
申请日：2014-12-26
申请人： Wistron NeWeb Corp.
发明人： Babak RADI , Yong-Jyun LU , Ming-Chi CHIU , Chien-Min HSU , Shih-Hong CHEN
IPC分类号： H05K1/09 , C23C14/48 , H01Q1/38 , C23C14/22 , H05K1/03 , H01B13/00 , C23C14/24
CPC分类号： H01Q1/38 , H01Q1/22 , H05K1/0326 , H05K1/0346 , H05K1/0353 , H05K3/048 , H05K3/146 , H05K3/16 , H05K3/381 , H05K2201/0129 , H05K2203/0769 , H05K2203/0783 , H05K2203/107 , H05K2203/1184 , H05K2203/308
摘要： A method for forming a patterned conductive structure is provided. The method includes forming a soluble layer on a surface of a substrate, wherein the soluble layer has an opening exposing a rough portion of the surface. A first conductive layer is formed on the soluble layer, wherein the first conductive layer extends onto the rough portion in the opening. The soluble layer and the first conductive layer on the soluble layer are removed, wherein a portion of the first conductive layer corresponding to the rough portion is remained on the substrate. A patterned conductive structure formed by the method is also provided.
摘要翻译：提供了一种用于形成图案化导电结构的方法。该方法包括在基底表面上形成可溶层，其中可溶层具有露出表面粗糙部分的开口。第一导电层形成在可溶层上，其中第一导电层延伸到开口中的粗糙部分上。可溶层和可溶层上的第一导电层被去除，其中对应于粗糙部分的第一导电层的一部分残留在基底上。还提供了通过该方法形成的图案化导电结构。

5. 发明申请

US20160104679A1 METHODS OF FORMING SUBSTRATE MICROVIAS WITH ANCHOR STRUCTURES 审中-公开
标题翻译：用锚固结构形成基底微结构的方法
公开(公告)号：US20160104679A1
公开(公告)日：2016-04-14
申请号：US14969406
申请日：2015-12-15
申请人： Intel Corporation
发明人： Sri Ranga Sai Boyapati , Qinglei Zhang
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/486 , H01L21/76805 , H01L21/76843 , H01L21/76865 , H01L21/76873 , H01L21/76877 , H01L21/76879 , H01L23/481 , H01L23/49866 , H01L2924/0002 , H05K3/002 , H05K3/4076 , H05K2201/2072 , H05K2203/1184 , H05K2203/1476 , H01L2924/00
摘要： Methods of forming anchor structures in package substrate microvias are described. Those methods and structures may include forming a titanium layer in an opening of a package substrate using a first deposition process, wherein the opening comprises an undercut region, and wherein the first conductive layer does not substantially form in an anchor region of the undercut region. The titanium layer may then be re-sputtered using a second deposition process, wherein the titanium layer is formed in the anchor region.
摘要翻译：描述了在封装衬底微孔中形成锚结构的方法。这些方法和结构可以包括使用第一沉积工艺在封装衬底的开口中形成钛层，其中开口包括底切区域，并且其中第一导电层基本上不形成在底切区域的锚定区域中。然后可以使用第二沉积工艺来重新溅射钛层，其中钛层形成在锚定区域中。

6. 发明授权

US09247644B2 Wiring board and method for manufacturing the same 有权
标题翻译：接线板及其制造方法
公开(公告)号：US09247644B2
公开(公告)日：2016-01-26
申请号：US14329062
申请日：2014-07-11
申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.
发明人： Kentaro Kaneko , Kazuhiro Kobayashi , Toshimitsu Omiya , Kotaro Kodani , Shunichiro Matsumoto , Ruofan Tang
IPC分类号： H05K1/03 , H05K1/09 , H05K1/00 , H05K7/10 , H05K1/11 , H05K3/34 , H05K3/24 , H05K3/38 , H05K3/46
CPC分类号： H05K1/113 , H05K3/244 , H05K3/3452 , H05K3/383 , H05K3/4682 , H05K2201/09472 , H05K2201/09745 , H05K2201/2072 , H05K2203/0152 , H05K2203/0307 , H05K2203/0376 , H05K2203/0384 , H05K2203/1184 , H05K2203/308
摘要： A wiring substrate includes an insulating layer, a pad, and a solder resist layer. The insulating layer has a first surface formed with a first recess portion. The pad is embedded in the first recess portion. The pad includes a second surface and a third surface. The third surface that is located at a lower position than the first surface so as to expose an inner wall surface of the first recess portion. The pad is formed with a second recess portion in a center portion of the third surface. The solder resist layer is provided on the first surface. An adjacent portion of the first surface to a peripheral portion of the first recess portion is smaller in roughness than a region of the first surface peripheral to the adjacent portion of the first surface.
摘要翻译：布线基板包括绝缘层，焊盘和阻焊层。绝缘层具有形成有第一凹部的第一表面。衬垫嵌入第一凹部。垫包括第二表面和第三表面。所述第三表面位于比所述第一表面更低的位置处，以暴露所述第一凹部的内壁表面。垫在第三表面的中心部分形成有第二凹部。阻焊层设置在第一表面上。所述第一表面与所述第一凹部的周边部分的相邻部分的粗糙度小于所述第一表面的相邻部分的周边的第一表面的区域。

7. 发明申请

US20150342050A1 ORIGAMI ENABLED MANUFACTURING SYSTEMS AND METHODS 有权
标题翻译： ORIGAMI启用的制造系统和方法
公开(公告)号：US20150342050A1
公开(公告)日：2015-11-26
申请号：US14761209
申请日：2014-01-15
申请人： ARIZONA BOARD OF REGENTS ACTING FPR AND ON BEHALF OF ARIZONA STATE UNIVERSITY
发明人： Hanqing Jiang , Hongyu Yu , Goran Konjevod , Yong Xu
IPC分类号： H05K1/14 , H05K1/18 , H05K1/02
CPC分类号： H05K1/028 , H01G11/78 , H01M2/204 , H01M6/40 , H01M6/42 , H01M10/0436 , H01M10/0525 , H01M10/0583 , H01M10/0585 , H01M10/425 , H05K1/0272 , H05K1/0278 , H05K1/0281 , H05K1/0283 , H05K1/148 , H05K1/181 , H05K2201/046 , H05K2201/05 , H05K2201/09036 , H05K2201/10015 , H05K2201/10037 , H05K2201/10098 , H05K2201/10113 , H05K2201/10128 , H05K2201/10151 , H05K2201/10174 , H05K2203/085 , H05K2203/087 , H05K2203/09 , H05K2203/1184 , H05K2203/302
摘要： An origami enabled manufacturing system. The system uses origami design principles to create functional materials, structures, devices and/or systems having an adjustable size and/or shape. An operational device can be coupled to a planar substrate shaped and sized to correspond to a desired origami shape of an origami pattern. A plurality of planar substrates can be coupled together by a plurality of connection members that corresponds to one or more crease of the origami pattern. An array of planar substrates can be formed that convert into a three dimensional structure with origami shape. The resulting three-dimensional structure provides smaller projection area, higher portability and deformability.
摘要翻译：具有折纸功能的制造系统。该系统使用折纸设计原理来创建具有可调节尺寸和/或形状的功能材料，结构，装置和/或系统。操作装置可以耦合到形状和尺寸对应于折纸图案的期望折纸形状的平面基板。可以通过对应于折纸图案的一个或多个折痕的多个连接构件将多个平面基板耦合在一起。可以形成平面基板的阵列，其转换成具有折纸形状的三维结构。所得到的三维结构提供较小的投影面积，更高的便携性和变形能力。

8. 发明申请

US20150092379A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150092379A1
公开(公告)日：2015-04-02
申请号：US14269585
申请日：2014-05-05
申请人： Mitsubishi Electric Corporation
发明人： Naoki YOSHIMATSU , Masayoshi SHINKAI , Taketoshi SHIKANO , Daisuke MURATA , Nobuyoshi KIMOTO , Yuji IMOTO , Mikio ISHIHARA
IPC分类号： H05K1/18 , H05K3/06 , H05K3/20 , H05K1/03
CPC分类号： H05K1/18 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/13055 , H05K1/0203 , H05K1/0306 , H05K3/06 , H05K3/20 , H05K3/284 , H05K2201/0373 , H05K2201/09036 , H05K2203/049 , H05K2203/1184 , H05K2203/1316 , Y10T29/41 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device according to the present invention includes a ceramic substrate, a plurality of circuit patterns arranged on a surface of the ceramic substrate, a semiconductor element arranged on an upper surface of at least one circuit pattern, and a sealing resin for sealing the ceramic substrate, the plurality of circuit patterns, and the semiconductor element, in which an undercut part is formed in opposed side surfaces of the circuit patterns adjacent to one another, the undercut part is configured such that an end of an upper surface of the circuit pattern protrudes outside the circuit pattern more than an end of a lower surface of the circuit pattern on the ceramic substrate, and the undercut part is also filled with the sealing resin.
摘要翻译：根据本发明的半导体器件包括陶瓷衬底，布置在陶瓷衬底的表面上的多个电路图案，布置在至少一个电路图案的上表面上的半导体元件和用于密封陶瓷的密封树脂衬底，多个电路图案和半导体元件，其中在相邻的电路图案的相对侧表面中形成底切部分，底切部分被构造成使得电路图案的上表面的端部突出在电路图案之外的多于陶瓷基板上的电路图案的下表面的端部，并且底切部分也填充有密封树脂。

9. 发明申请

US20150014027A1 WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：接线板及其制造方法
公开(公告)号：US20150014027A1
公开(公告)日：2015-01-15
申请号：US14329062
申请日：2014-07-11
申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.
发明人： Kentaro Kaneko , Kazuhiro Kobayashi , Toshimitsu Omiya , Kotaro Kodani , Shunichiro Matsumoto , Ruofan Tang
IPC分类号： H05K1/11 , H05K1/03
CPC分类号： H05K1/113 , H05K3/244 , H05K3/3452 , H05K3/383 , H05K3/4682 , H05K2201/09472 , H05K2201/09745 , H05K2201/2072 , H05K2203/0152 , H05K2203/0307 , H05K2203/0376 , H05K2203/0384 , H05K2203/1184 , H05K2203/308
摘要： A wiring substrate includes an insulating layer, a pad, and a solder resist layer. The insulating layer has a first surface formed with a first recess portion. The pad is embedded in the first recess portion. The pad includes a second surface and a third surface. The third surface that is located at a lower position than the first surface so as to expose an inner wall surface of the first recess portion. The pad is formed with a second recess portion in a center portion of the third surface. The solder resist layer is provided on the first surface. An adjacent portion of the first surface to a peripheral portion of the first recess portion is smaller in roughness than a region of the first surface peripheral to the adjacent portion of the first surface.
摘要翻译：布线基板包括绝缘层，焊盘和阻焊层。绝缘层具有形成有第一凹部的第一表面。衬垫嵌入第一凹部。垫包括第二表面和第三表面。所述第三表面位于比所述第一表面更低的位置处，以暴露所述第一凹部的内壁表面。垫在第三表面的中心部分形成有第二凹部。阻焊层设置在第一表面上。所述第一表面与所述第一凹部的周边部分的相邻部分的粗糙度小于所述第一表面的相邻部分的周边的第一表面的区域。

10. 发明授权

US08796691B2 System for displaying images and fabricating method thereof 有权
标题翻译：用于显示图像的系统及其制造方法
公开(公告)号：US08796691B2
公开(公告)日：2014-08-05
申请号：US12559181
申请日：2009-09-14
申请人： Chieh-Wen Lin , Chih-Chieh Wang , Sheng-Wen Chang , Te-Chang Wan
发明人： Chieh-Wen Lin , Chih-Chieh Wang , Sheng-Wen Chang , Te-Chang Wan
IPC分类号： H01L27/14
CPC分类号： H05K3/06 , G02F1/1345 , G02F1/13458 , H05K2201/0361 , H05K2203/1184
摘要： A system for displaying images and fabricating method thereof are provided. The system includes a thin film transistor substrate including a substrate having a display area and a pad area. The thin film transistor substrate further includes a conductive line disposed on the substrate in the display area. The conductive line includes a lower metal line, an upper metal line and a middle metal line therebetween. The width of the middle metal line is narrower than that of the upper metal line.
摘要翻译：提供一种用于显示图像的系统及其制造方法。该系统包括薄膜晶体管基板，其包括具有显示区域和焊盘区域的基板。薄膜晶体管基板还包括布置在显示区域中的基板上的导线。导线包括下金属线，上金属线和中间金属线。中间金属线的宽度比上金属线的宽度窄。

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