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1. 发明授权

US10326462B2 Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation 有权
公开(公告)号：US10326462B2
公开(公告)日：2019-06-18
申请号：US16154167
申请日：2018-10-08
申请人： Maxlinear, Inc.
发明人： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Gallagher
IPC分类号： H03M1/06 , H03M1/50 , H03M1/10 , H03M1/12 , H04L7/00 , H04L25/08 , H04W56/00
摘要： Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

2. 发明申请

US20190068227A1 OUTDOOR UNIT RESONATOR CORRECTION 审中-公开
公开(公告)号：US20190068227A1
公开(公告)日：2019-02-28
申请号：US16171463
申请日：2018-10-26
申请人： Maxlinear, Inc.
发明人： Subramanian Anantharaman Chandrasekarapuram , Anand Anandakumar , Stephane Laurent-Michel , Sheng Ye , Raja Pullela , Glenn Chang , Vamsi Paidi
IPC分类号： H04B1/10
摘要： A system comprises a microwave backhaul outdoor unit having a first resonant circuit, phase error determination circuitry, and phase error compensation circuitry. The first resonant circuit is operable to generate a first signal characterized by a first amount of phase noise and a first amount of temperature stability. The phase error determination circuitry is operable to generate a phase error signal indicative of phase error between the first signal and a second signal, wherein the second signal is characterized by a second amount of phase noise that is greater than the first amount of phase noise, and the second signal is characterized by a second amount of temperature instability that is less than the first amount of temperature instability. The phase error compensation circuitry is operable to adjust the phase of a data signal based on the phase error signal, the adjustment resulting in a phase compensated signal.

3. 发明申请

US20190020400A1 TRANSCEIVER ARRAY 审中-公开
公开(公告)号：US20190020400A1
公开(公告)日：2019-01-17
申请号：US16130644
申请日：2018-09-13
申请人： Maxlinear, Inc.
发明人： Curtis Ling , Sheng Ye
IPC分类号： H04B7/08 , H04B17/00 , H04B10/40 , H01Q3/24
摘要： Each of a plurality of modules comprises a respective one of a plurality of antenna elements, and each of a subset of the plurality of modules comprising a respective one of a plurality of transceivers, wherein the plurality of modules are interconnected via one or more communication links. The circuitry may be operable to receive a calibration signal via the plurality of antenna elements, determine, for each one of the antenna elements, a time and/or phase of arrival of the calibration signal, calculate, based on the time and/or phase of arrival of the calibration signal at each of the plurality of antenna elements, electrical distances between the plurality of antenna elements on the one or more communication links, and calculate beamforming coefficients for use with the plurality of antenna elements based on the electrical distances.

4. 发明授权

US09974025B2 Channel-sensitive power control 有权
公开(公告)号：US09974025B2
公开(公告)日：2018-05-15
申请号：US15464912
申请日：2017-03-21
申请人： Maxlinear, Inc.
发明人： James Qiu , Sridhar Ramesh , Sheng Ye , Curtis Ling
IPC分类号： H04W52/02 , H04B1/10 , H04L27/06 , H03G3/20 , H04L1/20 , H04W88/02 , H04B17/00
CPC分类号： H04W52/0245 , H03G3/20 , H04B1/109 , H04B17/00 , H04L1/20 , H04L27/06 , H04W88/02 , Y02D70/00 , Y02D70/40
摘要： A communication receiver which applies signal processing for quantitatively estimating receive signal factors such as communication channel quality, signal characteristics, and overall system received bit error rate (BER) or packet error rate (PER) and which applies a general algorithm for mapping these estimated factors to control receiver performance and minimize power consumption.

5. 发明授权

US09906227B2 Method and system for a sampled loop filter in a phase locked loop (PLL) 有权
公开(公告)号：US09906227B2
公开(公告)日：2018-02-27
申请号：US15236369
申请日：2016-08-12
申请人： Maxlinear, Inc.
发明人： Sangeetha Gopalakrishnan , Sheng Ye , Vamsi Paidi
IPC分类号： H03L7/00 , H03L7/085 , H03L7/197 , H03L7/093 , H03L7/099
CPC分类号： H03L7/085 , H03L7/093 , H03L7/099 , H03L7/1974 , H03L7/1976
摘要： Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

6. 发明授权

US09825640B2 Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation 有权
公开(公告)号：US09825640B2
公开(公告)日：2017-11-21
申请号：US15436088
申请日：2017-02-17
申请人： Maxlinear, Inc.
发明人： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Leo Gallagher
IPC分类号： H03M1/06 , H03M1/12 , H03M1/10 , H03M1/50 , H04W56/00
CPC分类号： H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
摘要： Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

7. 发明授权

US09537494B2 Reference-frequency-insensitive phase locked loop 有权
标题翻译：参考频率不敏感的锁相环
公开(公告)号：US09537494B2
公开(公告)日：2017-01-03
申请号：US14860262
申请日：2015-09-21
申请人： MaxLinear, Inc.
发明人： Sheng Ye
IPC分类号： H03L7/08 , H03L7/093 , H03L7/085 , H03L7/18
CPC分类号： H03L7/093 , H03L7/08 , H03L7/085 , H03L7/0891 , H03L7/18 , H03L2207/10
摘要： A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. A sampled loop filter (SLPF) in the phase locked loop may capture charge from a charge pump (CHP) in the phase locked loop and the charge is captured at a frequency corresponding to the frequency of the reference clock signal. A switch of the sampled loop filter is utilized and controlled to manage holding and releasing of the captured charge, where the switch is controlled utilizing a control signal. By utilizing the sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of the charge pump, disturbance which is associated with duty cycle errors of the crystal clock signal.
摘要翻译：锁相环可以用于利用倍频器产生频率为晶体时钟信号频率的两倍的参考时钟信号，并被键入晶体时钟信号的上升沿和下降沿。锁相环中的采样环路滤波器（SLPF）可以在锁相环中从电荷泵（CHP）捕获电荷，并以与参考时钟信号的频率对应的频率捕获电荷。利用和控制采样环路滤波器的开关来管理捕获的电荷的保持和释放，其中使用控制信号来控制开关。通过在锁相环中利用采样环路滤波器，锁相环可以在电荷泵的输出处消除与晶体时钟信号的占空比误差相关的干扰。

8. 发明申请

US20160285620A1 LOW-POWER ASYNCHRONOUS DATA LINKS 审中-公开
标题翻译：低功耗异步数据链路
公开(公告)号：US20160285620A1
公开(公告)日：2016-09-29
申请号：US15078601
申请日：2016-03-23
申请人： MaxLinear, Inc.
发明人： Sheng Ye
IPC分类号： H04L7/04 , H04L7/00
CPC分类号： H04L7/0079 , H04L7/0087 , H04L7/06
摘要： Systems and methods are provided for low-power asynchronous data links.
摘要翻译：为低功率异步数据链路提供了系统和方法。

9. 发明申请

US20160127119A1 OUTDOOR UNIT RESONATOR CORRECTION 有权
公开(公告)号：US20160127119A1
公开(公告)日：2016-05-05
申请号：US14976529
申请日：2015-12-21
申请人： Maxlinear, Inc.
发明人： Subramanian Anantharaman Chandrasekarapuram , Anand Anandakumar , Stephane Laurent-Michel , Sheng Ye , Raja Pullela , Glenn Chang , Vamsi Paidi
IPC分类号： H04L7/00
CPC分类号： H04B1/1027
摘要： A system comprises a microwave backhaul outdoor unit having a first resonant circuit, phase error determination circuitry, and phase error compensation circuitry. The first resonant circuit is operable to generate a first signal characterized by a first amount of phase noise and a first amount of temperature stability. The phase error determination circuitry is operable to generate a phase error signal indicative of phase error between the first signal and a second signal, wherein the second signal is characterized by a second amount of phase noise that is greater than the first amount of phase noise, and the second signal is characterized by a second amount of temperature instability that is less than the first amount of temperature instability. The phase error compensation circuitry is operable to adjust the phase of a data signal based on the phase error signal, the adjustment resulting in a phase compensated signal.

10. 发明申请

US20160043731A1 Method and system for Time Interleaved Analog-To-Digital Converter Timing Mismatch Estimation And Compensation 有权
标题翻译：时间交错模数转换器时序不匹配估计和补偿的方法和系统
公开(公告)号：US20160043731A1
公开(公告)日：2016-02-11
申请号：US14920699
申请日：2015-10-22
申请人： Maxlinear, Inc.
发明人： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumer , Sheng Ye , Timothy Leo Gallagher
IPC分类号： H03M1/06 , H03M1/10 , H03M1/12
CPC分类号： H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
摘要： Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
摘要翻译：用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号，以及通过估计期望的数字输出信号和阻塞信号之间的复数耦合系数，将在时间交错ADC中的定时偏移上的混叠在期望信号上的阻塞信号减少。解相关算法可以包括对称自适应去相关算法。所接收的模拟信号可以由芯片上的校准音发生器产生。混叠信号可以与来自乘法器的输出信号相加。复数耦合系数可以利用求和信号上的去相关算法来确定。乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。

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