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1. 发明授权

US07417902B2 Input circuit for a memory device, and a memory device and memory system employing the input circuit 有权
标题翻译：用于存储器件的输入电路，以及采用该输入电路的存储器件和存储器系统
公开(公告)号：US07417902B2
公开(公告)日：2008-08-26
申请号：US11325343
申请日：2006-01-05
申请人： Moon-Sook Park , Kyu-hyoun Kim
发明人： Moon-Sook Park , Kyu-hyoun Kim
IPC分类号： G11C7/06
CPC分类号： G11C7/1078 , G11C7/1084 , G11C2207/2254
摘要： In one embodiment, the input circuit includes a receiver circuit that generates a data signal based on a pair of differential data signals. A detecting circuit detects an offset voltage between the pair of differential data signals, and an adjusting circuit adjusts operation of the receiver to reduce a magnitude of the detected offset voltage based on the detected offset voltage.
摘要翻译：在一个实施例中，输入电路包括基于一对差分数据信号产生数据信号的接收器电路。检测电路检测一对差分数据信号之间的偏移电压，并且调整电路基于检测到的偏移电压来调整接收机的操作以减小检测到的偏移电压的幅度。

2. 发明申请

US20070008797A1 Data input and data output control device and method 有权
标题翻译：数据输入和数据输出控制装置及方法
公开(公告)号：US20070008797A1
公开(公告)日：2007-01-11
申请号：US11430281
申请日：2006-05-09
申请人： Moon-Sook Park , Kyu-Hyoun Kim
发明人： Moon-Sook Park , Kyu-Hyoun Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C5/066 , G11C7/1063 , G11C7/1066 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： A data input and data output control device and method in which a plurality of write or read data composed of m (2n+k) bits (where m, n, and k are all integers) may be accessed within one clock of external input clock.
摘要翻译：一种数据输入和数据输出控制装置和方法，其中由m（2＆gt; n + k）位（其中m，n和k都是整数）组成的多个写入或读取数据可以是在外部输入时钟的一个时钟内访问。

3. 发明申请

US20070109032A1 Charge pump circuit and method thereof 审中-公开
标题翻译：电荷泵电路及其方法
公开(公告)号：US20070109032A1
公开(公告)日：2007-05-17
申请号：US11598047
申请日：2006-11-13
申请人： Moon-Sook Park , Kyu-Hyoun Kim
发明人： Moon-Sook Park , Kyu-Hyoun Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0896 , H03L7/0812
摘要： A charge pump circuit and method thereof are provided. The example charge pump may include a first switch transistor supplying a first current to an output node in response to a first signal to increase a level of current at the output node, a second switch transistor sinking a second current from the output node in response to a second signal to decrease a level of current at the output node and a controller reducing an amount of the first and second currents if the first and second currents are generated concurrently. The example method may include supplying a first current to an output node in response to a first signal to increase a level of current at the output node, sinking a second current from the output node in response to a second signal to decrease a level of current at the output node and reducing an amount of the first and second currents if the first and second currents are generated concurrently.
摘要翻译：提供一种电荷泵电路及其方法。示例电荷泵可以包括响应于第一信号向输出节点提供第一电流以提高输出节点处的电流电平的第一开关晶体管，响应于第二开关晶体管从输出节点吸收第二电流第二信号，用于降低输出节点处的电流电平;以及控制器，如果同时产生第一和第二电流，则减少第一和第二电流的量。示例性方法可以包括响应于第一信号向输出节点提供第一电流以增加输出节点处的电流电平，响应于第二信号从输出节点吸收第二电流以降低电流电平并且如果同时产生第一和第二电流，则减少第一和第二电流的量。

4. 发明申请

US20070058454A1 Input circuit for a memory device, and a memory device and memory system employing the input circuit 有权
标题翻译：用于存储器件的输入电路，以及采用该输入电路的存储器件和存储器系统
公开(公告)号：US20070058454A1
公开(公告)日：2007-03-15
申请号：US11325343
申请日：2006-01-05
申请人： Moon-Sook Park , Kyu-hyoun Kim
发明人： Moon-Sook Park , Kyu-hyoun Kim
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1084 , G11C2207/2254
摘要： In one embodiment, the input circuit includes a receiver circuit that generates a data signal based on a pair of differential data signals. A detecting circuit detects an offset voltage between the pair of differential data signals, and an adjusting circuit adjusts operation of the receiver to reduce a magnitude of the detected offset voltage based on the detected offset voltage.
摘要翻译：在一个实施例中，输入电路包括基于一对差分数据信号产生数据信号的接收器电路。检测电路检测一对差分数据信号之间的偏移电压，并且调整电路基于检测到的偏移电压来调整接收机的操作以减小检测到的偏移电压的幅度。

5. 发明授权

US07522440B2 Data input and data output control device and method 有权
标题翻译：数据输入和数据输出控制装置及方法
公开(公告)号：US07522440B2
公开(公告)日：2009-04-21
申请号：US11430281
申请日：2006-05-09
申请人： Moon-Sook Park , Kyu-Hyoun Kim
发明人： Moon-Sook Park , Kyu-Hyoun Kim
IPC分类号： G11C5/02
CPC分类号： G11C7/1051 , G11C5/066 , G11C7/1063 , G11C7/1066 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： A data input and data output control device and method in which a plurality of write or read data composed of m (2n+k) bits (where m, n, and k are all integers) may be accessed within one clock of external input clock.
摘要翻译：一种数据输入和数据输出控制装置和方法，其中可以在外部输入时钟的一个时钟内访问由m（2n + k）位（其中m，n和k都是整数）组成的多个写入或读取数据。

6. 发明授权

US07420870B2 Phase locked loop circuit and method of locking a phase 有权
标题翻译：锁相环电路及锁相方法
公开(公告)号：US07420870B2
公开(公告)日：2008-09-02
申请号：US11430199
申请日：2006-05-09
申请人： Moon-Sook Park , Kyu-Hyoun Kim
发明人： Moon-Sook Park , Kyu-Hyoun Kim
IPC分类号： G11C8/02 , H03L7/06
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133 , H03L7/089 , H03L7/0891 , H03L7/093
摘要： A phase locked loop circuit and method of locking a phase. The phased locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal, a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal, and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer ≧4) internal clock signals. The phased locked loop circuit may also include a voltage controlled oscillator circuit, including at least four loops, receiving the control voltage and generating multiple internal clock signals.
摘要翻译：一种锁相环电路及锁相方法。相位锁定环电路可以包括接收外部时钟信号和反馈时钟信号的相位检测器，并且当外部时钟信号的相位引导反馈时钟信号的相位并在相位为外部时钟信号滞后于反馈时钟信号的相位，环路滤波器电路响应于上升信号增加控制电压，并响应于下降信号降低控制电压，以及压控振荡器电路接收控制电压和直接产生n个（其中n是整数> = 4）内部时钟信号。相位锁定环路电路还可以包括压控振荡器电路，其包括至少四个环路，接收控制电压并产生多个内部时钟信号。

7. 发明申请

US20060284657A1 Phase locked loop circuit and method of locking a phase 有权
标题翻译：锁相环电路及锁相方法
公开(公告)号：US20060284657A1
公开(公告)日：2006-12-21
申请号：US11430199
申请日：2006-05-09
申请人： Moon-Sook Park , Kyu-Hyoun Kim
发明人： Moon-Sook Park , Kyu-Hyoun Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133 , H03L7/089 , H03L7/0891 , H03L7/093
摘要： A phase locked loop circuit and method of locking a phase. The phased locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal, a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal, and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer ≧4) internal clock signals. The phased locked loop circuit may also include a voltage controlled oscillator circuit, including at least four loops, receiving the control voltage and generating multiple internal clock signals.
摘要翻译：一种锁相环电路及锁相方法。相位锁定环电路可以包括接收外部时钟信号和反馈时钟信号的相位检测器，并且当外部时钟信号的相位引导反馈时钟信号的相位并在相位为外部时钟信号滞后于反馈时钟信号的相位，环路滤波器电路响应于上升信号增加控制电压，并响应于下降信号降低控制电压，以及压控振荡器电路接收控制电压和直接产生n个（其中n是整数> = 4）内部时钟信号。相位锁定环路电路还可以包括压控振荡器电路，其包括至少四个环路，接收控制电压并产生多个内部时钟信号。

8. 发明授权

US07622971B2 Delay locked loop circuits and methods of generating clock signals 有权
标题翻译：延迟锁定环电路和产生时钟信号的方法
公开(公告)号：US07622971B2
公开(公告)日：2009-11-24
申请号：US11761464
申请日：2007-06-12
申请人： Moon-Sook Park , Young-Don Choi
发明人： Moon-Sook Park , Young-Don Choi
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/10 , H03L7/189
摘要： A delay locked loop circuit includes a phase detector configured to compare a phase of a reference clock signal with a phase of an output clock signal and to output a comparison signal, a control voltage generator configured to output a control voltage based on the comparison signal, a voltage controlled delay line comprising a plurality of delay elements and configured to delay the reference clock signal based on the control voltage and to output the output clock signal, and a control voltage initializer configured to generate digital codes based on characteristics of the voltage controlled delay line and to generate an initial control voltage based on the digital codes.
摘要翻译：延迟锁定环电路包括：相位检测器，被配置为将参考时钟信号的相位与输出时钟信号的相位进行比较并输出比较信号;控制电压发生器，被配置为基于比较信号输出控制电压; 电压控制延迟线，包括多个延迟元件，并且被配置为基于所述控制电压延迟所述参考时钟信号并输出所述输出时钟信号;以及控制电压初始化器，被配置为基于所述电压控制延迟的特性来生成数字代码并基于数字代码产生初始控制电压。

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