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    • 1. 发明申请
    • Rfid System
    • Rfid系统
    • US20080290997A1
    • 2008-11-27
    • US12158291
    • 2006-12-21
    • Nam Yun KimYong Hee LeeYoung Bin ChoJae Yeon ChoiSergeyev SergeyBelonozhkin Alexander
    • Nam Yun KimYong Hee LeeYoung Bin ChoJae Yeon ChoiSergeyev SergeyBelonozhkin Alexander
    • H04Q5/22
    • G06K7/0008G06K7/10039G06K7/10069
    • A radio frequency identification tag includes an antenna terminal, a memory, a D/A converter, a clock extractor, a frequency synthesizer, a radio frequency UP converter, and a power unit. An energy pumping signal is received and tag identification information is transmitted through the antenna terminal. The tag identification information is stored in the memory. The D/A converter converts the tag identification information into an analog signal in response to an information request signal included in the energy pumping signal. The clock extractor extracts a clock signal from the energy pumping signal. The frequency synthesizer is operated according to the clock signal of the clock extractor, and generates a frequency. The radio frequency up converter up-converts a signal output from the D/A converter, and allows the up-converted signal to be transmitted through the antenna terminal. The power unit supplies internal power.
    • 射频识别标签包括天线端子,存储器,D / A转换器,时钟提取器,频率合成器,射频UP转换器和功率单元。 接收能量泵送信号,通过天线端子发送标签识别信息。 标签识别信息存储在存储器中。 D / A转换器响应于包括在能量抽取信号中的信息请求信号,将标签识别信息转换成模拟信号。 时钟提取器从能量抽取信号中提取时钟信号。 频率合成器根据时钟提取器的时钟信号进行工作,并产生频率。 射频上变频器对从D / A转换器输出的信号进行上变频,并允许上变频信号通过天线端子传输。 电源单元提供内部电源。
    • 8. 发明申请
    • PHASE-LOCKED LOOP LOCK DETECT
    • 相位锁定锁定检测
    • US20120319747A1
    • 2012-12-20
    • US13164098
    • 2011-06-20
    • Ardeshir Namdar-MehdiabadiYong Hee LeeThomas Obkircher
    • Ardeshir Namdar-MehdiabadiYong Hee LeeThomas Obkircher
    • H03L7/095
    • H03L7/095H03L7/18
    • Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect. The reference multiplier can receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output generated by a VCO in a PLL from which the divider signal is generated. The reference multiplier can also generate a multiplied reference signal using the reference signal and the VCO output. The multiplied reference signal can have a frequency that is an integer multiple of a frequency of the reference signal. The lock detect can detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time.
    • 公开了一种用于检测锁相环(PLL)锁定的装置和方法。 一方面,锁定检测部件包括参考乘法器和锁定检测。 参考乘法器可以接收由PLL产生的VCO产生的分频器信号,分频器信号和由VCO产生的压控振荡器(VCO)输出。 参考乘法器还可以使用参考信号和VCO输出产生相乘的参考信号。 倍增的参考信号可以具有作为参考信号的频率的整数倍的频率。 锁定检测可以至少部分地基于将从延迟的参考信号产生的信号与从延迟的分频器信号产生的信号相比较预定的时间段来检测参考信号和分频器信号的锁相。