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1. 发明授权

US06986023B2 Conditional execution of coprocessor instruction based on main processor arithmetic flags 有权
标题翻译：基于主处理器算术标志的协处理器指令的有条件执行
公开(公告)号：US06986023B2
公开(公告)日：2006-01-10
申请号：US10215756
申请日：2002-08-09
申请人： Nigel C. Paver , William T. Maghielse , Wing K. Yu , Jianwei Liu , Anthony Jebson , Kailesh B. Bavaria , Rupal M. Parikh , Deli Deng , Mukesh Patel , Mark Fullerton , Murli Ganeshan , Stephen J. Strazdus
发明人： Nigel C. Paver , William T. Maghielse , Wing K. Yu , Jianwei Liu , Anthony Jebson , Kailesh B. Bavaria , Rupal M. Parikh , Deli Deng , Mukesh Patel , Mark Fullerton , Murli Ganeshan , Stephen J. Strazdus
IPC分类号： G06F15/16
CPC分类号： G06F9/30181 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30094 , G06F9/30101 , G06F9/30112 , G06F9/30145 , G06F9/3816 , G06F9/3824 , G06F9/3842 , G06F9/3877 , G06F9/3879 , G06F9/3885
摘要： A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.
摘要翻译：基于处理器的系统可以包括主处理器和协处理器。协处理器处理包括指定要由协处理器执行的数据处理操作的操作码的指令和用于识别用于协处理器指令的目标协处理器的协处理器标识字段。两位表示四个数据大小之一，包括一个字节（8位），一个半字（16位），一个字（32位）和一个双字（64位）。另外两个位表示饱和类型。

2. 发明授权

US07047393B2 Coprocessor processing instruction with coprocessor ID to broadcast main processor register data element to coprocessor multi-element register 有权
标题翻译：具有协处理器ID的协处理器处理指令，以将主处理器寄存器数据元件广播到协处理器多元件寄存器
公开(公告)号：US07047393B2
公开(公告)日：2006-05-16
申请号：US10263246
申请日：2002-10-02
申请人： Nigel C. Paver , Wing K. Yu , Murli Ganeshan
发明人： Nigel C. Paver , Wing K. Yu , Murli Ganeshan
IPC分类号： G06F9/315
CPC分类号： G06F9/30181 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30094 , G06F9/30101 , G06F9/30112 , G06F9/30145 , G06F9/3816 , G06F9/3824 , G06F9/3842 , G06F9/3877 , G06F9/3879 , G06F9/3885
摘要： A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type. A source register in the main processor and a destination register is in the coprocessor, those registers including data elements. The coprocessor instruction includes an opcode specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for the coprocessor instruction, the instruction to broadcast a data element from said source register to said destination register.
摘要翻译：基于处理器的系统可以包括主处理器和协处理器。协处理器处理包括指定要由协处理器执行的数据处理操作的操作码的指令和用于识别用于协处理器指令的目标协处理器的协处理器标识字段。两位表示四个数据大小之一，包括一个字节（8位），一个半字（16位），一个字（32位）和一个双字（64位）。另外两个位表示饱和类型。主处理器中的源寄存器和目标寄存器位于协处理器中，这些寄存器包括数据元素。协处理器指令包括指定由协处理器执行的数据处理操作的操作码和用于识别用于协处理器指令的目标协处理器的协处理器识别字段，将数据元素从所述源寄存器广播到所述目的地寄存器的指令。

3. 发明授权

US07356676B2 Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register 有权
标题翻译：从两个源寄存器提取对齐的数据，而不需要通过执行协处理器指令的模式位进行移位，用于从立即或寄存器导出偏移
公开(公告)号：US07356676B2
公开(公告)日：2008-04-08
申请号：US11351950
申请日：2006-02-10
申请人： Nigel C. Paver , Wing K. Yu , Murli Ganeshan
发明人： Nigel C. Paver , Wing K. Yu , Murli Ganeshan
IPC分类号： G06F9/312
CPC分类号： G06F9/30036 , G06F9/30032
摘要： A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a coprocessor targetted by the coprocessor instructions. After determining whether to alternatively load source values into a respective one of two source registers, new source values are transferred to one or more of the source registers. The coprocessor executes the coprocessor instruction, which includes an offset information, to extract values from the source registers based on the offset information and places the values in a destination register.
摘要翻译：基于处理器的系统可以包括主处理器和协处理器。协处理器处理包括指定要由协处理器执行的数据处理操作的操作码的指令和用于识别由协处理器指令指定的协处理器的协处理器标识字段。在确定是否将源值交替地加载到两个源寄存器中的相应一个源寄存器中之后，新的源值被传送到一个或多个源寄存器。协处理器执行包括偏移信息的协处理器指令，以基于偏移信息从源寄存器提取值，并将值放在目的地寄存器中。

4. 发明申请

US20120249200A1 DIGITALLY CONTROLLED DELAY LINES WITH FINE GRAIN AND COARSE GRAIN DELAY ELEMENTS, AND METHODS AND SYSTEMS TO ADJUST IN FINE GRAIN INCREMENTS 有权
标题翻译：具有精细粒度和粗粒度延迟元素的数字控制延迟线，以及调整细粒度变化的方法和系统
公开(公告)号：US20120249200A1
公开(公告)日：2012-10-04
申请号：US13078609
申请日：2011-04-01
申请人： Wing K. Yu
发明人： Wing K. Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/0818
摘要： Digitally controllable delay lines including fine grain and coarse grain delay elements, and methods and system to calibrate the delay lines in fine grain increments. Calibration may include calibrating a number of fine grain elements for which a combined delay is substantially equal to a delay of a coarse grain element, and calibrating numbers of fine grain and coarse grain elements which a combined delay corresponds to a period of a reference clock. A digitally controlled delay line may be implemented as part of a digital delay locked loop (DLL), and calibration parameters may be provided to a slave DLL having a similarly implemented delay line. A digitally controllable DLL may provide relatively low-power, high-resolution over a spectrum of process, voltage, and temperature variations, and may be implemented in relatively high-speed applications previously reserved for analog DLLs.
摘要翻译：数字可控延迟线，包括细晶粒和粗粒延迟元件，以及以细晶粒增量校准延迟线的方法和系统。校准可以包括校准多个细晶粒元素，其中组合延迟基本上等于粗晶粒元素的延迟，以及校准细晶粒和粗晶粒元素的数目，合并延迟对应于参考时钟的周期。数字控制的延迟线可以被实现为数字延迟锁定环（DLL）的一部分，并且校准参数可以被提供给具有类似实现的延迟线的从动DLL。数字可控DLL可以在过程，电压和温度变化的频谱上提供相对低功率，高分辨率，并且可以在先前为模拟DLL保留的相对高速的应用中实现。

5. 发明授权

US06226216B1 Sectional column activated memory 有权
标题翻译：分段列激活内存
公开(公告)号：US06226216B1
公开(公告)日：2001-05-01
申请号：US09489096
申请日：2000-01-21
申请人： Wing K. Yu
发明人： Wing K. Yu
IPC分类号： G11C800
CPC分类号： G11C11/418 , G11C11/419
摘要： A memory may include sectional columns so that groups of cells on the same column but coupled to different word lines may be selectively accessed. As a result, only a portion of the cells of a given column is activated at any given time. The remainder of the column may be decoupled, thereby reducing the need to charge up or discharge the rest of the column. Because only a smaller portion of the column is charged or discharged, the lower capacitance associated with a lower number of cells may result in a speed and power consumption improvement.
摘要翻译：存储器可以包括分段列，使得可以选择性地访问同一列上但耦合到不同字线的单元组。结果，给定列的单元的仅一部分在任何给定的时间被激活。塔的剩余部分可以去耦合，从而减少对塔的其余部分充电或排出的需要。由于只有较小部分的列被充电或放电，与较小数量的单元相关联的较低电容可能会导致速度和功耗改善。

6. 发明授权

US08564345B2 Digitally controlled delay lines with fine grain and coarse grain delay elements, and methods and systems to adjust in fine grain increments 有权
标题翻译：具有细粒度和粗粒延迟元件的数字控制延迟线，以及以细晶粒增量调节的方法和系统
公开(公告)号：US08564345B2
公开(公告)日：2013-10-22
申请号：US13078609
申请日：2011-04-01
申请人： Wing K. Yu
发明人： Wing K. Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/0818
摘要： Digitally controllable delay lines including fine grain and coarse grain delay elements, and methods and system to calibrate the delay lines in fine grain increments. Calibration may include calibrating a number of fine grain elements for which a combined delay is substantially equal to a delay of a coarse grain element, and calibrating numbers of fine grain and coarse grain elements which a combined delay corresponds to a period of a reference clock. A digitally controlled delay line may be implemented as part of a digital delay locked loop (DLL), and calibration parameters may be provided to a slave DLL having a similarly implemented delay line. A digitally controllable DLL may provide relatively low-power, high-resolution over a spectrum of process, voltage, and temperature variations, and may be implemented in relatively high-speed applications previously reserved for analog DLLs.
摘要翻译：数字可控延迟线，包括细晶粒和粗粒延迟元件，以及以细晶粒增量校准延迟线的方法和系统。校准可以包括校准多个细晶粒元素，其中组合延迟基本上等于粗晶粒元素的延迟，以及校准细晶粒和粗晶粒元素的数目，合并延迟对应于参考时钟的周期。数字控制的延迟线可以被实现为数字延迟锁定环（DLL）的一部分，并且校准参数可以被提供给具有类似实现的延迟线的从动DLL。数字可控DLL可以在过程，电压和温度变化的频谱上提供相对低功率，高分辨率，并且可以在先前为模拟DLL保留的相对高速的应用中实现。

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