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1. 发明申请

US20130015850A1 Die-Sized Atomic Magnetometer and Method of Forming the Magnetometer 有权
标题翻译：模具原子磁强计和形成磁强计的方法
公开(公告)号：US20130015850A1
公开(公告)日：2013-01-17
申请号：US13182510
申请日：2011-07-14
申请人： Philipp Lindorfer , Peter J. Hopper , William French , Paul Mawson , Steven Hunt , Roozbeh Parsa
发明人： Philipp Lindorfer , Peter J. Hopper , William French , Paul Mawson , Steven Hunt , Roozbeh Parsa
IPC分类号： G01R33/02 , H01L43/12 , H01L31/02 , G01N21/59 , H01L29/02 , H01L21/50 , H01S3/02 , G01J1/42 , H01L29/82 , H01L31/18
CPC分类号： G01R33/0052 , G01J1/4228 , G01J1/44 , G01J5/20 , G01R33/032 , H01L31/18 , H01L43/12 , H01L2224/04105 , H01L2224/18 , H01L2224/19 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/82 , H01L2224/92244 , H01L2924/15153 , H01S5/0208 , H01S5/0222 , H01S5/026 , H01S5/0261 , H01S5/0262 , H01S5/183
摘要： The cost and size of an atomic magnetometer are reduced by attaching together a first die which integrates together a vapor cell, top and side photo detectors, and processing electronics, a second die which integrates together an optics package and a heater for the vapor cell, and a third die which integrates together a VCSEL, a heater for the VCSEL, and control electronics.
摘要翻译：原子磁强计的成本和尺寸通过将集成在一起的蒸气单元，顶部和侧面光电检测器以及处理电子器件的第一模具连接在一起来降低，第二模具将光学组件和用于蒸气室的加热器集成在一起，以及将VCSEL，VCSEL的加热器和控制电子器件集成在一起的第三管芯。

2. 发明授权

US09201124B2 Die-sized atomic magnetometer and method of forming the magnetometer 有权
标题翻译：模具尺寸的原子磁强计和形成磁力计的方法
公开(公告)号：US09201124B2
公开(公告)日：2015-12-01
申请号：US13182510
申请日：2011-07-14
申请人： Philipp Lindorfer , Peter J. Hopper , William French , Paul Mawson , Steven Hunt , Roozbeh Parsa
发明人： Philipp Lindorfer , Peter J. Hopper , William French , Paul Mawson , Steven Hunt , Roozbeh Parsa
IPC分类号： G01R33/02 , G01R33/032 , G01J1/44 , G01J5/20 , G01J1/42 , H01S5/026 , H01S5/183
CPC分类号： G01R33/0052 , G01J1/4228 , G01J1/44 , G01J5/20 , G01R33/032 , H01L31/18 , H01L43/12 , H01L2224/04105 , H01L2224/18 , H01L2224/19 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/82 , H01L2224/92244 , H01L2924/15153 , H01S5/0208 , H01S5/0222 , H01S5/026 , H01S5/0261 , H01S5/0262 , H01S5/183
摘要： The cost and size of an atomic magnetometer are reduced by attaching together a first die which integrates together a vapor cell, top and side photo detectors, and processing electronics, a second die which integrates together an optics package and a heater for the vapor cell, and a third die which integrates together a VCSEL, a heater for the VCSEL, and control electronics.
摘要翻译：原子磁强计的成本和尺寸通过将集成在一起的蒸气单元，顶部和侧面光电检测器以及处理电子器件的第一模具连接在一起来降低，第二模具将光学组件和用于蒸气室的加热器集成在一起，以及将VCSEL，VCSEL的加热器和控制电子器件集成在一起的第三管芯。

3. 发明申请

US20130176703A1 Thermally-Insulated Micro-Fabricated Atomic Clock Structure and Method of Forming the Atomic Clock Structure 有权
标题翻译：热绝缘微制造原子钟结构和形成原子钟结构的方法
公开(公告)号：US20130176703A1
公开(公告)日：2013-07-11
申请号：US13345688
申请日：2012-01-07
申请人： Peter J. Hopper , William French , Paul Mawson , Steven Hunt , Roozbeh Parsa , Martin Fallon , Ann Gabrys , Andrei Papou
发明人： Peter J. Hopper , William French , Paul Mawson , Steven Hunt , Roozbeh Parsa , Martin Fallon , Ann Gabrys , Andrei Papou
IPC分类号： H05K7/00 , H01L31/0224 , H01L31/18
CPC分类号： H01L31/024 , G04F5/14 , H01L31/00 , H01L31/022408 , H01L31/103 , H01L31/18 , H01L31/1804 , H03L7/26 , Y02E10/547
摘要： A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to −40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.
摘要翻译：微制造的原子钟结构是绝热的，使得原子钟结构可以在外部温度下降到-40℃的环境中以非常小的功率运行，同时保持适当的温度 VCSEL和蒸汽池内的气体的操作。

4. 发明授权

US09024397B2 Thermally-insulated micro-fabricated atomic clock structure and method of forming the atomic clock structure 有权
标题翻译：绝热微制造原子钟结构及形成原子钟结构的方法
公开(公告)号：US09024397B2
公开(公告)日：2015-05-05
申请号：US13345688
申请日：2012-01-07
申请人： Peter J. Hopper , William French , Paul Mawson , Steven Hunt , Roozbeh Parsa , Martin Fallon , Ann Gabrys , Andrei Papou
发明人： Peter J. Hopper , William French , Paul Mawson , Steven Hunt , Roozbeh Parsa , Martin Fallon , Ann Gabrys , Andrei Papou
IPC分类号： H01L31/0224 , H01L31/18 , G01R33/02 , G04F5/14 , H01L31/00 , H01L31/103 , H03L7/26
CPC分类号： H01L31/024 , G04F5/14 , H01L31/00 , H01L31/022408 , H01L31/103 , H01L31/18 , H01L31/1804 , H03L7/26 , Y02E10/547
摘要： A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to −40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.
摘要翻译：微制造的原子钟结构是绝热的，使得原子钟结构可以在外部温度下降到-40℃的环境中以非常小的功率运行，同时保持适当的温度 VCSEL和蒸汽池内的气体的操作。

5. 发明授权

US08836327B2 Micro-fabricated atomic magnetometer and method of forming the magnetometer 有权
标题翻译：微型原子磁强计及形成磁力计的方法
公开(公告)号：US08836327B2
公开(公告)日：2014-09-16
申请号：US13314097
申请日：2011-12-07
申请人： William French , Philipp Lindorfer , Peter J. Hopper , Roozbeh Parsa , Andrew James West , Byron Jon Roderick Shulver
发明人： William French , Philipp Lindorfer , Peter J. Hopper , Roozbeh Parsa , Andrew James West , Byron Jon Roderick Shulver
IPC分类号： G01R33/02
CPC分类号： G01R33/032 , H01L24/16 , H01L2224/131 , H01L2224/16145 , H01L2924/12042 , H01L2924/12043 , H01L2924/014 , H01L2924/00
摘要： The cost and size of an atomic magnetometer are reduced by attaching a vapor cell structure that has a vapor cell cavity to a base die that has a laser light source that outputs light to the vapor cell cavity, and attaching a photo detection die that has a photodiode to the vapor cell structure to detect light from the laser light source that passes through the vapor cell cavity.
摘要翻译：原子磁力计的成本和尺寸通过将具有蒸汽单元空腔的蒸汽单元结构附接到具有将光输出到蒸气腔空腔的激光源的基座上而被降低，以及附接具有光电二极管到蒸汽池结构以检测来自通过蒸气室腔的激光源的光。

6. 发明申请

US20130147472A1 Micro-Fabricated Atomic Magnetometer and Method of Forming the Magnetometer 有权
标题翻译：微制造原子磁强计和形成磁力计的方法
公开(公告)号：US20130147472A1
公开(公告)日：2013-06-13
申请号：US13314097
申请日：2011-12-07
申请人： William French , Philipp Lindorfer , Peter J. Hopper , Roozbeh Parsa , Andrew James West , Byron Jon Roderick Shulver
发明人： William French , Philipp Lindorfer , Peter J. Hopper , Roozbeh Parsa , Andrew James West , Byron Jon Roderick Shulver
IPC分类号： G01R33/02 , H01L21/58 , H01L29/82
CPC分类号： G01R33/032 , H01L24/16 , H01L2224/131 , H01L2224/16145 , H01L2924/12042 , H01L2924/12043 , H01L2924/014 , H01L2924/00
摘要： The cost and size of an atomic magnetometer are reduced by attaching a vapor cell structure that has a vapor cell cavity to a base die that has a laser light source that outputs light to the vapor cell cavity, and attaching a photo detection die that has a photodiode to the vapor cell structure to detect light from the laser light source that passes through the vapor cell cavity.
摘要翻译：原子磁力计的成本和尺寸通过将具有蒸汽单元空腔的蒸汽单元结构附接到具有将光输出到蒸气腔空腔的激光源的基座上而被降低，以及附接具有光电二极管到蒸汽池结构以检测来自通过蒸气室腔的激光源的光。

7. 发明授权

US07978519B2 Method of reading an NVM cell that utilizes a gated diode 有权
标题翻译：读取利用门控二极管的NVM单元的方法
公开(公告)号：US07978519B2
公开(公告)日：2011-07-12
申请号：US12884567
申请日：2010-09-17
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and drain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and is separated therefrom by intervening dielectric material, the method comprising: biasing the deep N-type well at a preselected read voltage; holding the source region of the PMOS transistor at the read voltage; holding the drain of the PMOS transistor at ground; and holding the control gate at ground for a preselected read time.
摘要翻译：一种读取在N型半导体材料的深阱中形成的NVM单元结构的方法，其中所述NVM单元结构包括形成在N型阱中的PMOS晶体管，所述PMOS晶体管包括间隔开的p型源极和漏极区域，其间形成n型沟道区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，所述NMOS晶体管包括间隔开的n型源极和漏极区，其限定p型沟道导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分通过插入电介质材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其分离，该方法com 奖励：以预选的读取电压偏置深N型阱; 将PMOS晶体管的源极区域保持在读取电压; 将PMOS晶体管的漏极保持在地; 并将控制门保持在地面以进行预选的读取时间。

8. 发明申请

US20110007574A1 METHOD OF ERASING AN NVM CELL THAT UTILIZES A GATED DIODE 有权
标题翻译：消除使用栅极二极管的NVM电池的方法
公开(公告)号：US20110007574A1
公开(公告)日：2011-01-13
申请号：US12884519
申请日：2010-09-17
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing the deep N-type well at a selected erase voltage; holding the source and drain regions of the PMOS transistor at the erase voltage or floating; and holding the control gate at ground for a preselected erase time.
摘要翻译：一种擦除形成在N型半导体材料的深阱中的NVM单元结构的方法，其中NVM单元结构包括形成在N型阱中的PMOS晶体管，PMOS晶体管包括间隔开的p型源极和漏极在它们之间限定n型沟道区的区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，NMOS晶体管包括间隔开的n型源和限定p型沟道的雨区导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分通过插入介电材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其隔开，包括：在所选择的擦除电压下偏置所述深N型阱; 将PMOS晶体管的源极和漏极区域保持在擦除电压或浮置; 并将控制门保持在地面以进行预先选择的擦除时间。

9. 发明授权

US07969790B2 Method of erasing an NVM cell that utilizes a gated diode 有权
标题翻译：擦除使用门控二极管的NVM单元的方法
公开(公告)号：US07969790B2
公开(公告)日：2011-06-28
申请号：US12884519
申请日：2010-09-17
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing the deep N-type well at a selected erase voltage; holding the source and drain regions of the PMOS transistor at the erase voltage or floating; and holding the control gate at ground for a preselected erase time.
摘要翻译：一种擦除形成在N型半导体材料的深阱中的NVM单元结构的方法，其中NVM单元结构包括形成在N型阱中的PMOS晶体管，PMOS晶体管包括间隔开的p型源极和漏极在它们之间限定n型沟道区的区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，NMOS晶体管包括间隔开的n型源和限定p型沟道的雨区导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分通过插入介电材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其隔开，包括：在所选择的擦除电压下偏置所述深N型阱; 将PMOS晶体管的源极和漏极区域保持在擦除电压或浮置; 并将控制门保持在地面以进行预先选择的擦除时间。

10. 发明申请

US20110007570A1 METHOD OF READING AN NVM CELL THAT UTILIZES A GATED DIODE 有权
标题翻译：读取使用栅极二极管的NVM电池的方法
公开(公告)号：US20110007570A1
公开(公告)日：2011-01-13
申请号：US12884567
申请日：2010-09-17
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and drain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and is separated therefrom by intervening dielectric material, the method comprising: biasing the deep N-type well at a preselected read voltage; holding the source region of the PMOS transistor at the read voltage; holding the drain of the PMOS transistor at ground; and holding the control gate at ground for a preselected read time.
摘要翻译：一种读取在N型半导体材料的深阱中形成的NVM单元结构的方法，其中所述NVM单元结构包括形成在N型阱中的PMOS晶体管，所述PMOS晶体管包括间隔开的p型源极和漏极区域，其间形成n型沟道区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，所述NMOS晶体管包括间隔开的n型源极和漏极区，其限定p型沟道导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分通过插入电介质材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其分离，该方法com 奖励：以预选的读取电压偏置深N型阱; 将PMOS晶体管的源极区域保持在读取电压; 将PMOS晶体管的漏极保持在地; 并将控制门保持在地面以进行预选的读取时间。

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