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1. 发明申请

US20100042772A1 Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cells 失效
标题翻译：用于多级闪存单元中高可靠性数据存储和检索操作的方法和装置
公开(公告)号：US20100042772A1
公开(公告)日：2010-02-18
申请号：US12228795
申请日：2008-08-14
申请人： Randy M. Bonella , Daniel J. Allen , Thomas J. Holman , Chung W. Lam , Hiroyuki Sakamoto
发明人： Randy M. Bonella , Daniel J. Allen , Thomas J. Holman , Chung W. Lam , Hiroyuki Sakamoto
IPC分类号： G06F12/12 , G11C16/00 , G11C16/06 , G06F12/08
CPC分类号： G11C11/5628 , G11C2211/5641
摘要： One or more multi-level NAND flash cells are operated so as to store only single-level data, and these operations achieve an increased level of charge separation between the data states of the single-level operation by requiring a write to both the upper and lower pages, even though only one bit of data is being stored. That is, the second write operation increases the difference in floating gate charge between the erased state and the programmed state of the first write operation without changing the data in the flash memory cell. In one embodiment, a controller instructs the flash memory to perform two write operations for storing a single bit of data in an MLC flash cell. In another embodiment, the flash memory recognizes that a single write operation is directed a high reliability memory area and internally generates the required plurality of programming steps to place at least a predetermined amount of charge on the specified floating gate.
摘要翻译：操作一个或多个多电平NAND闪存单元以仅存储单级数据，并且这些操作通过要求写入上层和第二级的单级操作来实现单级操作的数据状态之间的电荷分离水平的提高即使只有一位数据被存储，也是较低的页面。也就是说，第二写入操作增加擦除状态和第一写操作的编程状态之间的浮栅电荷的差异，而不改变闪存单元中的数据。在一个实施例中，控制器指示闪速存储器执行用于在MLC闪存单元中存储单个数据位的两个写入操作。在另一个实施例中，闪速存储器识别出单个写入操作被引导到高可靠性存储区域，并且在内部产生所需的多个编程步骤以将至少预定量的电荷放置在指定的浮动栅极上。

2. 发明授权

US07941592B2 Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cells 失效
标题翻译：用于多级闪存单元中高可靠性数据存储和检索操作的方法和装置
公开(公告)号：US07941592B2
公开(公告)日：2011-05-10
申请号：US12228795
申请日：2008-08-14
申请人： Randy M. Bonella , Daniel J. Allen , Thomas J. Holman , Chung W. Lam , Hiroyuki Sakamoto
发明人： Randy M. Bonella , Daniel J. Allen , Thomas J. Holman , Chung W. Lam , Hiroyuki Sakamoto
IPC分类号： G06F12/00
CPC分类号： G11C11/5628 , G11C2211/5641
摘要： One or more multi-level NAND flash cells are operated so as to store only single-level data, and these operations achieve an increased level of charge separation between the data states of the single-level operation by requiring a write to both the upper and lower pages, even though only one bit of data is being stored. That is, the second write operation increases the difference in floating gate charge between the erased state and the programmed state of the first write operation without changing the data in the flash memory cell. In one embodiment, a controller instructs the flash memory to perform two write operations for storing a single bit of data in an MLC flash cell. In another embodiment, the flash memory recognizes that a single write operation is directed a high reliability memory area and internally generates the required plurality of programming steps to place at least a predetermined amount of charge on the specified floating gate.
摘要翻译：操作一个或多个多电平NAND闪存单元以仅存储单级数据，并且这些操作通过要求写入上层和第二级的单级操作来实现单级操作的数据状态之间的电荷分离水平的提高即使只有一位数据被存储，也是较低的页面。也就是说，第二写入操作增加擦除状态和第一写操作的编程状态之间的浮栅电荷的差异，而不改变闪存单元中的数据。在一个实施例中，控制器指示闪速存储器执行用于在MLC闪存单元中存储单个数据位的两个写入操作。在另一个实施例中，闪速存储器识别出单个写入操作被引导到高可靠性存储区域，并且在内部产生所需的多个编程步骤以将至少预定量的电荷放置在指定的浮动栅极上。

3. 发明授权

US07894502B2 Spread spectrum clock signal generation system and method 有权
标题翻译：扩频时钟信号发生系统及方法
公开(公告)号：US07894502B2
公开(公告)日：2011-02-22
申请号：US12165689
申请日：2008-07-01
申请人： Adam L. Carley , Daniel J. Allen
发明人： Adam L. Carley , Daniel J. Allen
IPC分类号： H04B1/00
CPC分类号： G06F1/08
摘要： A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal. The programmable modulator is coupled to an arbitrary waveform synthesizer that generates timing for edges of the clock signal based on the edge position values. A variety of modulations can be imposed on the clock signal using these techniques, including triangle wave modulation, near-triangle modulation, random and pseudo-random modulation.
摘要翻译：一种用于产生具有扩频调制的时钟信号的系统和方法。该方法涉及通过从针对每个边缘的定时的数字表示产生时钟信号的边缘的边缘位置来产生时钟信号，以将扩频调制传递给时钟信号。提供了一种可编程调制器，其基于时变周期值和时变占空比值中的至少一个，生成表示时钟信号的边沿的边缘位置的数字值。可编程调制器可以包括产生时变数字周期值的称为周期调制电路的第一电路和产生时变数字占空比值的称为占空比调制电路的第二电路。处理时变周期值和时变占空比值以产生指定时钟信号的边沿位置的数字边沿位置值。可编程调制器耦合到任意波形合成器，其基于边缘位置值产生时钟信号的边沿的定时。使用这些技术可以对时钟信号施加各种调制，包括三角波调制，近三角调制，随机和伪随机调制。

4. 发明授权

US07424046B2 Spread spectrum clock signal generation system and method 有权
标题翻译：扩频时钟信号发生系统及方法
公开(公告)号：US07424046B2
公开(公告)日：2008-09-09
申请号：US10964777
申请日：2004-10-15
申请人： Adam L. Carley , Daniel J. Allen
发明人： Adam L. Carley , Daniel J. Allen
IPC分类号： H04B1/00
CPC分类号： G06F1/08
摘要： A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal. The programmable modulator is coupled to an arbitrary waveform synthesizer that generates timing for edges of the clock signal based on the edge position values. A variety of modulations can be imposed on the clock signal using these techniques, including triangle wave modulation, near-triangle modulation, random and pseudo-random modulation.
摘要翻译：一种用于产生具有扩频调制的时钟信号的系统和方法。该方法涉及通过从针对每个边缘的定时的数字表示产生时钟信号的边缘的边缘位置来产生时钟信号，以将扩频调制传递给时钟信号。提供了一种可编程调制器，其基于时变周期值和时变占空比值中的至少一个，生成表示时钟信号的边沿的边缘位置的数字值。可编程调制器可以包括产生时变数字周期值的称为周期调制电路的第一电路和产生时变数字占空比值的称为占空比调制电路的第二电路。处理时变周期值和时变占空比值以产生指定时钟信号的边沿位置的数字边沿位置值。可编程调制器耦合到任意波形合成器，其基于边缘位置值产生时钟信号的边沿的定时。使用这些技术可以对时钟信号施加各种调制，包括三角波调制，近三角调制，随机和伪随机调制。

5. 发明授权

US06522365B1 Method and system for pixel clock recovery 有权
标题翻译：像素时钟恢复方法和系统
公开(公告)号：US06522365B1
公开(公告)日：2003-02-18
申请号：US09491761
申请日：2000-01-27
申请人： Vladimir Levantovsky , Daniel J. Allen
发明人： Vladimir Levantovsky , Daniel J. Allen
IPC分类号： H04N506
CPC分类号： G09G5/008 , H04N5/126
摘要： A method of recovering a pixel clock for generating a digital image from an analog video signal is presented. The on and off-transition times for the active video portion of a digital image and the image size defined in a video standard are used to generate a pixel clock. The analog video signal is digitized according to the pixel clock and the image size of the resulting digital image is compared with the image size defined in the video standard. The pixel clock frequency is adjusted in response to the image size comparison. The optimum phase of the pixel clock relative to the analog video signal is determined through a repetitive phase adjustment technique. A first image coordinate is determined for a pixel clock at one phase and a subsequent image coordinate is determined for a pixel clock after decrementing the phase of the pixel clock. The first image coordinate and the subsequent image are compared. If the coordinates are not equal, the steps of decrementing the phase of the pixel clock and determining a corresponding image coordinate are repeated until equal coordinates are determined. The phase of the pixel clock is then adjusted by a predetermined value to yield an optimum phase.
摘要翻译：提出了从模拟视频信号中恢复生成数字图像的像素时钟的方法。使用数字图像的活动视频部分的开和关转换时间以及视频标准中定义的图像大小来生成像素时钟。根据像素时钟将模拟视频信号数字化，并将所得数字图像的图像大小与视频标准中定义的图像大小进行比较。响应于图像尺寸比较来调整像素时钟频率。通过重复相位调整技术确定像素时钟相对于模拟视频信号的最佳相位。对于一个相位的像素时钟确定第一图像坐标，并且在递减像素时钟的相位之后为像素时钟确定后续图像坐标。比较第一图像坐标和后续图像。如果坐标不相等，则重复降低像素时钟的相位并确定对应的图像坐标的步骤，直到确定相等的坐标。然后将像素时钟的相位调整预定值以产生最佳相位。

6. 发明授权

US08008975B1 Gate-boosted, variable voltage supply rail amplifier 有权
标题翻译：门极升压，可变电源电源轨放大器
公开(公告)号：US08008975B1
公开(公告)日：2011-08-30
申请号：US12415788
申请日：2009-03-31
申请人： Daniel J. Allen , Eric J. Swanson , Scott A. Woodford
发明人： Daniel J. Allen , Eric J. Swanson , Scott A. Woodford
IPC分类号： H03F3/04
CPC分类号： H03F3/3022 , H03F1/0216 , H03F3/45475 , H03F2200/513
摘要： In at least one embodiment, an electronic system includes an amplifier having an on-chip charge pump to provide a gate boost voltage to boost a gate voltage of at least one on-chip field effect transistor (FET) of an output stage of an amplifier. In at least one embodiment, the gate boost voltage boosts the gate voltage higher than the supply voltage rail to increase an overdrive voltage of the on-chip FET. In at least one embodiment, the gate boost voltage boosts the DC bias of an input signal and, thus, generation of gate boost voltage by the on-chip charge pump is signal-independent, i.e. independent of the input signal. Increasing the overdrive voltage increases the efficiency of the amplifier by decreasing the difference between the maximum swing of the output voltage and the voltage supply rails of the at least one on-chip FET relative to conventional designs.
摘要翻译：在至少一个实施例中，电子系统包括具有片上电荷泵的放大器，以提供栅极升压电压以升高放大器的输出级的至少一个片上场效应晶体管（FET）的栅极电压。在至少一个实施例中，栅极升压电压将栅极电压升高高于电源电压轨，以增加片上FET的过驱动电压。在至少一个实施例中，栅极升压电压升高输入信号的DC偏置，因此片上电荷泵的栅极升压电压的产生与信号无关，即独立于输入信号。通过减小输出电压的最大摆动和至少一个片上FET的电压供应轨之间的差异，相对于常规设计，增加过驱动电压增加了放大器的效率。

7. 发明申请

US20080273574A1 SPREAD SPECTRUM CLOCK SIGNAL GENERATION SYSTEM AND METHOD 有权
标题翻译：传播频谱信号发生系统和方法
公开(公告)号：US20080273574A1
公开(公告)日：2008-11-06
申请号：US12165689
申请日：2008-07-01
申请人： Adam L. Carley , Daniel J. Allen
发明人： Adam L. Carley , Daniel J. Allen
IPC分类号： H04B1/69
CPC分类号： G06F1/08
摘要： A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal. The programmable modulator is coupled to an arbitrary waveform synthesizer that generates timing for edges of the clock signal based on the edge position values. A variety of modulations can be imposed on the clock signal using these techniques, including triangle wave modulation, near-triangle modulation, random and pseudo-random modulation.
摘要翻译：一种用于产生具有扩频调制的时钟信号的系统和方法。该方法涉及通过从针对每个边缘的定时的数字表示产生时钟信号的边缘的边缘位置来产生时钟信号，以将扩频调制传递给时钟信号。提供了一种可编程调制器，其基于时变周期值和时变占空比值中的至少一个，生成表示时钟信号的边沿的边缘位置的数字值。可编程调制器可以包括产生时变数字周期值的称为周期调制电路的第一电路和产生时变数字占空比值的称为占空比调制电路的第二电路。处理时变周期值和时变占空比值以产生指定时钟信号的边沿位置的数字边沿位置值。可编程调制器耦合到任意波形合成器，其基于边缘位置值产生时钟信号的边沿的定时。使用这些技术可以对时钟信号施加各种调制，包括三角波调制，近三角调制，随机和伪随机调制。

8. 发明授权

US06366292B1 Scaling method and apparatus for a flat panel display 有权
标题翻译：用于平板显示器的缩放方法和装置
公开(公告)号：US06366292B1
公开(公告)日：2002-04-02
申请号：US09338011
申请日：1999-06-22
申请人： Daniel J. Allen
发明人： Daniel J. Allen
IPC分类号： G09G536
CPC分类号： G06T3/403
摘要： A method and apparatus for the scaling of digital image data for improved image quality on LCD displays is described. An output pixel value is determined from a source pixel array approximately centered at the output pixel location. Edge arrays are generated by comparing the differences in the color component values of adjacent vertical and horizontal pixels to a threshold value. Logic arrays operate on edge arrays to determine if the source pixel array matches predetermined pixel arrangements. Offset values corresponding to the location of the output pixel relative to the center pixel in the source pixel array are calculated. The offset values are modified if a logic array match is found. Offset values are also modified according to a predetermined modifier function. Bilinear interpolation based on the resulting offset values is used to determine the output pixel value.
摘要翻译：描述了用于缩放用于在LCD显示器上提高图像质量的数字图像数据的方法和装置。输出像素值从大致以输出像素位置为中心的源像素阵列确定。通过将相邻垂直和水平像素的颜色分量值的差异与阈值进行比较来生成边缘阵列。逻辑阵列在边缘阵列上操作以确定源像素阵列是否匹配预定的像素排列。计算对应于输出像素相对于源像素阵列中的中心像素的位置的偏移值。如果发现逻辑阵列匹配，则修改偏移值。偏移值也根据预定的修正函数进行修改。使用基于所得到的偏移值的双线性插值来确定输出像素值。

9. 发明授权

US06266154B1 Grayscale enhancement system and method 失效
标题翻译：灰度增强系统和方法
公开(公告)号：US06266154B1
公开(公告)日：2001-07-24
申请号：US09082628
申请日：1998-05-21
申请人： Daniel J. Allen
发明人： Daniel J. Allen
IPC分类号： H04N1405
CPC分类号： H04N1/40075 , H04N1/4055
摘要： A grayscale enhancement system which operates on color or monochrome source halftone images to produce output halftone cells of the same visual weight but spatially distributed to reduce artifacts caused by limited grayscale levels. By operating upon a set of input halftone cells surrounding each output pixel cell with a set of logic operations implementing unique algorithms, the system re-distributes the weight of the halftone cells characterizing inferred-halftone cells. A rendering subsystem, responsive to the inferred-halftones, then produces signal for driving an output device to the best of the output device's ability.
摘要翻译：一种灰度增强系统，其操作在彩色或单色源半色调图像上以产生相同视觉重量但是空间分布的输出半色调单元，以减少由有限的灰度级别引起的伪影。通过利用实现独特算法的一组逻辑运算来操作围绕每个输出像素单元的一组输入半色调单元，系统重新分配表征推测半色调单元的半色调单元的重量。渲染子系统响应于推断的半色调，然后产生用于驱动输出设备的信号以达到输出设备的最佳能力。

10. 发明授权

US07613263B2 Clock and data recovery method and apparatus 失效
标题翻译：时钟和数据恢复方法和装置
公开(公告)号：US07613263B2
公开(公告)日：2009-11-03
申请号：US10793149
申请日：2004-03-04
申请人： Daniel J. Allen
发明人： Daniel J. Allen
IPC分类号： H04L7/00
CPC分类号： H03L7/00 , H03L7/087 , H03L7/091 , H03L7/093 , H03L2207/50 , H04L7/0008 , H04L7/0331 , H04L7/0337 , H04L7/0338
摘要： A method and circuit for processing a serial data stream carrying data at a rate established by an underlying clock signal, the method and circuit involving: time-stamping each of the transitions of a sequence of transitions within the serial data stream to thereby generate a sequence of time stamps; and based at least in part on the sequence of time-stamps, recovering the data from the serial data stream.
摘要翻译：一种用于处理以由底层时钟信号建立的速率承载数据的串行数据流的方法和电路，所述方法和电路涉及：对串行数据流内的一系列转换的每个转换进行时间戳，从而产生序列的时间戳; 并且至少部分地基于时间戳的顺序，从串行数据流中恢复数据。

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