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1. 发明申请

US20080140993A1 FETCH ENGINE MONITORING DEVICE AND METHOD THEREOF 审中-公开
标题翻译： FETCH发动机监控装置及其方法
公开(公告)号：US20080140993A1
公开(公告)日：2008-06-12
申请号：US11608691
申请日：2006-12-08
申请人： Ravindra N. Bhargava , Benjamin T. Sander , David Neal Suggs
发明人： Ravindra N. Bhargava , Benjamin T. Sander , David Neal Suggs
IPC分类号： G06F9/312
CPC分类号： G06F11/3419 , G06F11/3471 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： In accordance with a specific embodiment of the present disclosure, hardware periodically monitors a fetch cycle that fetches data associated with an address to determine performance parameters associated with the fetch cycle. Information related to the duration of a fetch cycle is maintained as well as information indicating the occurrence of various states and data values related to the fetch cycle. For example, the virtual address being processed during the fetch cycle is saved at the integrated circuit containing the fetch engine. Other performance-related parameters associated with execution of instructions at an execution engine of the pipeline are also monitored periodically. However, monitoring performance of the fetch engine is decoupled from monitoring performance-related events of the execution engine.
摘要翻译：根据本公开的具体实施例，硬件周期性地监视取出周期，其获取与地址相关联的数据，以确定与获取周期相关联的性能参数。与获取周期的持续时间相关的信息被保持，以及指示与获取周期相关的各种状态和数据值的发生的信息。例如，在获取循环期间处理的虚拟地址被保存在包含提取引擎的集成电路中。与流水线的执行引擎上的指令执行相关联的其他与性能相关的参数也被周期性地监视。然而，提取引擎的监视性能与监视与执行引擎的性能相关的事件分离。

2. 发明申请

US20080141008A1 EXECUTION ENGINE MONITORING DEVICE AND METHOD THEREOF 审中-公开
标题翻译：执行发动机监控装置及其方法
公开(公告)号：US20080141008A1
公开(公告)日：2008-06-12
申请号：US11608700
申请日：2006-12-08
申请人： Benjamin T. Sander , Michael Edward Tuuk , Ravindra N. Bhargava
发明人： Benjamin T. Sander , Michael Edward Tuuk , Ravindra N. Bhargava
IPC分类号： G06F9/312
CPC分类号： G06F9/30043
摘要： In accordance with a specific embodiment of the present disclosure, hardware periodically monitors a fetch cycle that fetches data associated with an address to determine performance parameters associated with the fetch cycle. Information related to the duration of a fetch cycle is maintained as well as information indicating the occurrence of various states and data values related to the fetch cycle. For example, the virtual address being processed during the fetch cycle is saved at the integrated circuit containing the fetch engine. Other performance-related parameters associated with execution of instructions at an execution engine of the pipeline are also monitored periodically. However, monitoring performance of the fetch engine is decoupled from monitoring performance-related events of the execution engine.
摘要翻译：根据本公开的具体实施例，硬件周期性地监视取出周期，其获取与地址相关联的数据，以确定与获取周期相关联的性能参数。与获取周期的持续时间相关的信息被保持，以及指示与获取周期相关的各种状态和数据值的发生的信息。例如，在读取周期期间正在处理的虚拟地址被保存在包含提取引擎的集成电路中。与流水线的执行引擎上的指令执行相关联的其他与性能相关的参数也被周期性地监视。然而，提取引擎的监视性能与监视与执行引擎的性能相关的事件分离。

3. 发明申请

US20080141002A1 INSTRUCTION PIPELINE MONITORING DEVICE AND METHOD THEREOF 审中-公开
标题翻译：指导管道监测装置及其方法
公开(公告)号：US20080141002A1
公开(公告)日：2008-06-12
申请号：US11608697
申请日：2006-12-08
申请人： Ravindra N. Bhargava , Benjamin T. Sander
发明人： Ravindra N. Bhargava , Benjamin T. Sander
IPC分类号： G06F9/38
CPC分类号： G06F12/1036 , G06F9/3867 , G06F11/3476 , G06F11/348 , G06F2201/86 , G06F2212/681
摘要： In accordance with a specific embodiment of the present disclosure, hardware periodically monitors a fetch cycle that fetches data associated with an address to determine performance parameters associated with the fetch cycle. Information related to the duration of a fetch cycle is maintained as well as information indicating the occurrence of various states and data values related to the fetch cycle. For example, the virtual address being processed during the fetch cycle is saved at the integrated circuit containing the fetch engine. Other performance-related parameters associated with execution of instructions at an execution engine of the pipeline are also monitored periodically. However, monitoring performance of the fetch engine is decoupled from monitoring performance-related events of the execution engine.
摘要翻译：根据本公开的具体实施例，硬件周期性地监视取出周期，其获取与地址相关联的数据，以确定与获取周期相关联的性能参数。与获取周期的持续时间相关的信息被保持，以及指示与获取周期相关的各种状态和数据值的发生的信息。例如，在读取周期期间正在处理的虚拟地址被保存在包含提取引擎的集成电路中。与流水线的执行引擎上的指令执行相关联的其他与性能相关的参数也被周期性地监视。然而，提取引擎的监视性能与监视与执行引擎的性能相关的事件分离。

4. 发明申请

US20090164766A1 BRANCH HISTORY WITH POLYMORPHIC INDIRECT BRANCH INFORMATION 有权
标题翻译：分支历史与多态间接分支信息
公开(公告)号：US20090164766A1
公开(公告)日：2009-06-25
申请号：US11961511
申请日：2007-12-20
申请人： David Suggs , Ravindra N. Bhargava
发明人： David Suggs , Ravindra N. Bhargava
IPC分类号： G06F9/38
CPC分类号： G06F9/3848
摘要： A system and method for efficient improvement of branch prediction in a microprocessor with negligible impact on die-area, power consumption, and clock cycle period. It is determined if a program counter (PC) register contains a polymorphic indirect unconditional branch (PIUB) instruction. One determination may be searching a table with a portion or all of a PC of past PIUB instructions. If a hit occurs in this table, the global shift register (GSR) is updated by shifting a portion of the branch target address into the GSR, rather than updating the GSR with a taken/not-taken prediction bit. The stored value in the GSR is input into a hashing function along with the PC in order to index prediction tables such as a pattern history table (PHT), a branch target buffer (BTB), an indirect target array, or other. The updated value due to the PIUB instruction improves the accuracy of the prediction tables.
摘要翻译：一种用于在微处理器中有效改进分支预测的系统和方法，对芯片面积，功耗和时钟周期周期的影响可以忽略不计。确定程序计数器（PC）寄存器是否包含多态间接无条件分支（PIUB）指令。一个决定可能是搜索具有过去PIUB指令的PC的一部分或全部的表。如果在该表中发生命中，则通过将分支目标地址的一部分移动到GSR中来更新全局移位寄存器（GSR），而不是使用采取/未采用的预测位来更新GSR。将GSR中的存储值与PC一起输入散列函数，以便对诸如模式历史表（PHT），分支目标缓冲器（BTB），间接目标阵列等之类的预测表进行索引。由PIUB指令引起的更新值提高了预测表的准确性。

5. 发明申请

US20120117362A1 REPLAY OF DETECTED PATTERNS IN PREDICTED INSTRUCTIONS 有权
标题翻译：检测图案在预测指示中的重置
公开(公告)号：US20120117362A1
公开(公告)日：2012-05-10
申请号：US12943859
申请日：2010-11-10
申请人： Ravindra N. Bhargava , David Suggs , Anthony X. Jarvis
发明人： Ravindra N. Bhargava , David Suggs , Anthony X. Jarvis
IPC分类号： G06F9/38
CPC分类号： G06F9/3848 , G06F9/381
摘要： Techniques are disclosed relating to improving the performance of branch prediction in processors. In one embodiment, a processor is disclosed that includes a branch prediction unit configured to predict a sequence of instructions to be issued by the processor for execution. The processor also includes a pattern detection unit configured to detect a pattern in the predicted sequence of instructions, where the pattern includes a plurality of predicted instructions. In response to the pattern detection unit detecting the pattern, the processor is configured to switch from issuing instructions predicted by the branch prediction unit to issuing the plurality of instructions. In some embodiments, the processor includes a replay unit that is configured to replay fetch addresses to an instruction fetch unit to cause the plurality of predicted instructions to be issued.
摘要翻译：公开了关于改善处理器中分支预测的性能的技术。在一个实施例中，公开了一种处理器，其包括分支预测单元，其被配置为预测要由处理器发出的用于执行的指令序列。所述处理器还包括：图案检测单元，被配置为检测所述预测指令序列中的图案，其中所述图案包括多个预测指令。响应于图案检测单元检测图案，处理器被配置为从由分支预测单元预测的发布指令切换到发出多个指令。在一些实施例中，处理器包括重播单元，其被配置为将取指地址重播到指令提取单元以使得发出多个预测指令。

6. 发明授权

US08782384B2 Branch history with polymorphic indirect branch information 有权
标题翻译：具有多态间接分支信息的分支历史
公开(公告)号：US08782384B2
公开(公告)日：2014-07-15
申请号：US11961511
申请日：2007-12-20
申请人： David Suggs , Ravindra N. Bhargava
发明人： David Suggs , Ravindra N. Bhargava
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3848
摘要： A system and method for efficient improvement of branch prediction in a microprocessor with negligible impact on die-area, power consumption, and clock cycle period. It is determined if a program counter (PC) register contains a polymorphic indirect unconditional branch (PIUB) instruction. One determination may be searching a table with a portion or all of a PC of past PIUB instructions. If a hit occurs in this table, the global shift register (GSR) is updated by shifting a portion of the branch target address into the GSR, rather than updating the GSR with a taken/not-taken prediction bit. The stored value in the GSR is input into a hashing function along with the PC in order to index prediction tables such as a pattern history table (PHT), a branch target buffer (BTB), an indirect target array, or other. The updated value due to the PIUB instruction improves the accuracy of the prediction tables.
摘要翻译：一种用于在微处理器中有效改进分支预测的系统和方法，对芯片面积，功耗和时钟周期周期的影响可以忽略不计。确定程序计数器（PC）寄存器是否包含多态间接无条件分支（PIUB）指令。一个决定可能是搜索具有过去PIUB指令的PC的一部分或全部的表。如果在该表中发生命中，则通过将分支目标地址的一部分移动到GSR中来更新全局移位寄存器（GSR），而不是使用采取/未采用的预测位来更新GSR。将GSR中的存储值与PC一起输入散列函数，以便对诸如模式历史表（PHT），分支目标缓冲器（BTB），间接目标阵列等之类的预测表进行索引。由PIUB指令引起的更新值提高了预测表的准确性。

7. 发明授权

US08667257B2 Detecting branch direction and target address pattern and supplying fetch address by replay unit instead of branch prediction unit 有权
标题翻译：检测分支方向和目标地址模式，并通过重播单元而不是分支预测单元提供提取地址
公开(公告)号：US08667257B2
公开(公告)日：2014-03-04
申请号：US12943859
申请日：2010-11-10
申请人： Ravindra N. Bhargava , David Suggs , Anthony X. Jarvis
发明人： Ravindra N. Bhargava , David Suggs , Anthony X. Jarvis
IPC分类号： G06F9/38
CPC分类号： G06F9/3848 , G06F9/381
摘要： Techniques are disclosed relating to improving the performance of branch prediction in processors. In one embodiment, a processor is disclosed that includes a branch prediction unit configured to predict a sequence of instructions to be issued by the processor for execution. The processor also includes a pattern detection unit configured to detect a pattern in the predicted sequence of instructions, where the pattern includes a plurality of predicted instructions. In response to the pattern detection unit detecting the pattern, the processor is configured to switch from issuing instructions predicted by the branch prediction unit to issuing the plurality of instructions. In some embodiments, the processor includes a replay unit that is configured to replay fetch addresses to an instruction fetch unit to cause the plurality of predicted instructions to be issued.
摘要翻译：公开了关于改善处理器中分支预测的性能的技术。在一个实施例中，公开了一种处理器，其包括分支预测单元，其被配置为预测要由处理器发出的用于执行的指令序列。所述处理器还包括：图案检测单元，被配置为检测所述预测指令序列中的图案，其中所述图案包括多个预测指令。响应于图案检测单元检测图案，处理器被配置为从由分支预测单元预测的发布指令切换到发出多个指令。在一些实施例中，处理器包括重播单元，其被配置为将取指地址重播到指令提取单元以使得发出多个预测指令。

8. 发明申请

US20080209190A1 PARALLEL PREDICTION OF MULTIPLE BRANCHES 审中-公开
标题翻译：并行预测多分支
公开(公告)号：US20080209190A1
公开(公告)日：2008-08-28
申请号：US11680043
申请日：2007-02-28
申请人： Ravindra N. Bhargava , Brian Raf
发明人： Ravindra N. Bhargava , Brian Raf
IPC分类号： G06F9/38
CPC分类号： G06F9/3844
摘要： A branch history value associated with a first branch instruction of a first set of instructions is determined. The branch history value represents a branch history of a program flow prior to the first branch instruction. A first branch prediction of the first branch instruction is determined based on the branch history value of the first branch instruction and a first identifier associated with first branch instruction. A second branch prediction of a second branch instruction of the first set of instructions based on the branch history value associated with the first branch instruction and a second identifier associated with the second branch instruction. The second branch instruction occurs subsequent to the first branch instruction in the program flow. A second set of instructions is fetched at the processing device based on at least one of the first branch prediction and the second branch prediction.
摘要翻译：确定与第一组指令的第一分支指令相关联的分支历史值。分支历史值表示在第一分支指令之前的程序流的分支历史。基于第一分支指令的分支历史值和与第一分支指令相关联的第一标识符来确定第一分支指令的第一分支预测。基于与第一分支指令相关联的分支历史值和与第二分支指令相关联的第二标识符，对第一组指令的第二分支指令进行第二分支预测。第二分支指令在程序流中的第一分支指令之后发生。基于第一分支预测和第二分支预测中的至少一个，在处理装置处获取第二组指令。

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