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1. 发明申请

US20080140993A1 FETCH ENGINE MONITORING DEVICE AND METHOD THEREOF 审中-公开
标题翻译： FETCH发动机监控装置及其方法
公开(公告)号：US20080140993A1
公开(公告)日：2008-06-12
申请号：US11608691
申请日：2006-12-08
申请人： Ravindra N. Bhargava , Benjamin T. Sander , David Neal Suggs
发明人： Ravindra N. Bhargava , Benjamin T. Sander , David Neal Suggs
IPC分类号： G06F9/312
CPC分类号： G06F11/3419 , G06F11/3471 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： In accordance with a specific embodiment of the present disclosure, hardware periodically monitors a fetch cycle that fetches data associated with an address to determine performance parameters associated with the fetch cycle. Information related to the duration of a fetch cycle is maintained as well as information indicating the occurrence of various states and data values related to the fetch cycle. For example, the virtual address being processed during the fetch cycle is saved at the integrated circuit containing the fetch engine. Other performance-related parameters associated with execution of instructions at an execution engine of the pipeline are also monitored periodically. However, monitoring performance of the fetch engine is decoupled from monitoring performance-related events of the execution engine.
摘要翻译：根据本公开的具体实施例，硬件周期性地监视取出周期，其获取与地址相关联的数据，以确定与获取周期相关联的性能参数。与获取周期的持续时间相关的信息被保持，以及指示与获取周期相关的各种状态和数据值的发生的信息。例如，在获取循环期间处理的虚拟地址被保存在包含提取引擎的集成电路中。与流水线的执行引擎上的指令执行相关联的其他与性能相关的参数也被周期性地监视。然而，提取引擎的监视性能与监视与执行引擎的性能相关的事件分离。

2. 发明申请

US20080141008A1 EXECUTION ENGINE MONITORING DEVICE AND METHOD THEREOF 审中-公开
标题翻译：执行发动机监控装置及其方法
公开(公告)号：US20080141008A1
公开(公告)日：2008-06-12
申请号：US11608700
申请日：2006-12-08
申请人： Benjamin T. Sander , Michael Edward Tuuk , Ravindra N. Bhargava
发明人： Benjamin T. Sander , Michael Edward Tuuk , Ravindra N. Bhargava
IPC分类号： G06F9/312
CPC分类号： G06F9/30043
摘要： In accordance with a specific embodiment of the present disclosure, hardware periodically monitors a fetch cycle that fetches data associated with an address to determine performance parameters associated with the fetch cycle. Information related to the duration of a fetch cycle is maintained as well as information indicating the occurrence of various states and data values related to the fetch cycle. For example, the virtual address being processed during the fetch cycle is saved at the integrated circuit containing the fetch engine. Other performance-related parameters associated with execution of instructions at an execution engine of the pipeline are also monitored periodically. However, monitoring performance of the fetch engine is decoupled from monitoring performance-related events of the execution engine.
摘要翻译：根据本公开的具体实施例，硬件周期性地监视取出周期，其获取与地址相关联的数据，以确定与获取周期相关联的性能参数。与获取周期的持续时间相关的信息被保持，以及指示与获取周期相关的各种状态和数据值的发生的信息。例如，在读取周期期间正在处理的虚拟地址被保存在包含提取引擎的集成电路中。与流水线的执行引擎上的指令执行相关联的其他与性能相关的参数也被周期性地监视。然而，提取引擎的监视性能与监视与执行引擎的性能相关的事件分离。

3. 发明申请

US20080141002A1 INSTRUCTION PIPELINE MONITORING DEVICE AND METHOD THEREOF 审中-公开
标题翻译：指导管道监测装置及其方法
公开(公告)号：US20080141002A1
公开(公告)日：2008-06-12
申请号：US11608697
申请日：2006-12-08
申请人： Ravindra N. Bhargava , Benjamin T. Sander
发明人： Ravindra N. Bhargava , Benjamin T. Sander
IPC分类号： G06F9/38
CPC分类号： G06F12/1036 , G06F9/3867 , G06F11/3476 , G06F11/348 , G06F2201/86 , G06F2212/681
摘要： In accordance with a specific embodiment of the present disclosure, hardware periodically monitors a fetch cycle that fetches data associated with an address to determine performance parameters associated with the fetch cycle. Information related to the duration of a fetch cycle is maintained as well as information indicating the occurrence of various states and data values related to the fetch cycle. For example, the virtual address being processed during the fetch cycle is saved at the integrated circuit containing the fetch engine. Other performance-related parameters associated with execution of instructions at an execution engine of the pipeline are also monitored periodically. However, monitoring performance of the fetch engine is decoupled from monitoring performance-related events of the execution engine.
摘要翻译：根据本公开的具体实施例，硬件周期性地监视取出周期，其获取与地址相关联的数据，以确定与获取周期相关联的性能参数。与获取周期的持续时间相关的信息被保持，以及指示与获取周期相关的各种状态和数据值的发生的信息。例如，在读取周期期间正在处理的虚拟地址被保存在包含提取引擎的集成电路中。与流水线的执行引擎上的指令执行相关联的其他与性能相关的参数也被周期性地监视。然而，提取引擎的监视性能与监视与执行引擎的性能相关的事件分离。

4. 发明授权

US07937569B1 System and method for scheduling operations using speculative data operands 有权
标题翻译：使用推测数据操作数调度操作的系统和方法
公开(公告)号：US07937569B1
公开(公告)日：2011-05-03
申请号：US10839471
申请日：2004-05-05
申请人： Benjamin T. Sander , Brian D. McMinn
发明人： Benjamin T. Sander , Brian D. McMinn
IPC分类号： G06F9/30
CPC分类号： G06F9/3826 , G06F9/3834 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： A system and method for scheduling operations using speculative data operands. In one embodiment, a system may include a scheduler configured to store a speculative source tag and a non-speculative source tag for an operand of an operation and an execution core configured to execute operations issued by the scheduler and to output result tags identifying operands generated by executing the operations. The scheduler may be configured to determine whether the operation is ready to issue by comparing the speculative source tag, but not the non-speculative source tag, to the result tags output by the execution core unless an incorrect speculation has been detected. If an incorrect speculation has been detected, the scheduler may be configured to determine whether the operation is ready to issue by comparing the non-speculative source tag, but not the speculative source tag, to the result tags output by the execution core.
摘要翻译：一种用于使用推测数据操作数调度操作的系统和方法。在一个实施例中，系统可以包括调度器，其被配置为存储用于操作的操作数的推测源标签和非推测性源标签，以及被配置为执行由调度器发出的操作的执行核心，并输出标识所生成的操作数的结果标签通过执行操作。调度器可以被配置为通过将推测源标签而不是非推测性源标签与执行核心输出的结果标签进行比较来确定操作是否准备好发布，除非检测到不正确的猜测。如果检测到不正确的猜测，则调度器可以被配置为通过将非推测性源标签而不是推测源标签与执行核心输出的结果标签进行比较来确定操作是否准备发布。

5. 发明授权

US07315935B1 Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots 有权
标题翻译：基于功能单元发布槽在寄存器文件中进行端口仲裁的装置和方法
公开(公告)号：US07315935B1
公开(公告)日：2008-01-01
申请号：US10679745
申请日：2003-10-06
申请人： Mitchell Alsup , Brian D. McMinn , Benjamin T. Sander , David E. Kroesche
发明人： Mitchell Alsup , Brian D. McMinn , Benjamin T. Sander , David E. Kroesche
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3836 , G06F9/30141 , G06F9/3828 , G06F9/3889
摘要： A microprocessor is configured to provide port arbitration in a register file. The microprocessor includes a plurality of functional units configured to collectively operate on a maximum number of operands in a given execution cycle, and a register file providing a number of read ports that is insufficient to provide the maximum number of operands to the plurality of functional units in the given execution cycle. The microprocessor also includes an arbitration logic coupled to allocate the read ports of the register file for use by selected functional units during the given execution cycle.
摘要翻译：微处理器被配置为在寄存器文件中提供端口仲裁。微处理器包括多个功能单元，其被配置为在给定执行周期中对最大数目的操作数进行集中操作;以及寄存器文件，其提供不足以向多个功能单元提供最大数目的操作数的多个读取端口在给定的执行周期。微处理器还包括一个仲裁逻辑，它被耦合以分配该寄存器文件的读取端口，供所选功能单元在给定的执行周期中使用。

6. 发明授权

US06823427B1 Sectored least-recently-used cache replacement 有权
标题翻译：构造最近最近使用的缓存替换
公开(公告)号：US06823427B1
公开(公告)日：2004-11-23
申请号：US09859271
申请日：2001-05-16
申请人： Benjamin T. Sander , Teik-Chung Tan , Adam Duley
发明人： Benjamin T. Sander , Teik-Chung Tan , Adam Duley
IPC分类号： G06F1200
CPC分类号： G06F12/128 , G06F12/0864
摘要： Various methods and systems for implementing a sectored least recently used (LRU) cache replacement algorithm are disclosed. Each set in an N-way set-associative cache is partitioned into several sectors that each include two or more of the N ways. Usage status indicators such as pointers show the relative usage status of the sectors in an associated set. For example, an LRU pointer may point to the LRU sector, an MRU pointer may point to the MRU sector, and so on. When a replacement is performed, a way within the LRU sector identified by the LRU pointer is filled.
摘要翻译：公开了用于实现最近最少使用的（LRU）高速缓存替换算法的各种方法和系统。 N路组合关联高速缓存中的每个集合被划分成几个扇区，每个扇区包括N个方式中的两个或更多个。使用状态指示器（如指针）显示相关组中扇区的相对使用状态。例如，LRU指针可以指向LRU扇区，MRU指针可以指向MRU扇区，依此类推。当执行替换时，由LRU指针识别的LRU扇区内的方式被填充。

7. 发明授权

US06408364B1 Apparatus and method for implementing a least recently used cache replacement algorithm 失效
标题翻译：用于实现最近最少使用的高速缓存替换算法的装置和方法
公开(公告)号：US06408364B1
公开(公告)日：2002-06-18
申请号：US09528041
申请日：2000-03-17
申请人： Teik-Chang Tan , Leonel Lozano , Benjamin T. Sander
发明人： Teik-Chang Tan , Leonel Lozano , Benjamin T. Sander
IPC分类号： G06F1200
CPC分类号： G06F12/123
摘要： A least recently used (LRU) cache replacement algorithm is implemented with a set of N pointer registers that point to respective ways of an N-way set of memory blocks. One of the pointer registers is an LRU pointer, pointing to a least recently used way and another of the pointer registers is a most recently used (MRU) pointer, pointing to a most recently used way. For a cache fill operation in which a new memory block is written to one of the N ways, the new memory block is written into the way (wayn), pointed to by the LRU pointer. All the pointers except the MRU pointer are promoted to point to a way pointed to by respective newer neighboring pointers, the newer neighboring pointers being neighbors towards the MRU pointer. The MRU pointer is updated to point to the wayn in which the new memory block was written. For a cache hit in which one of the memory blocks in the set, waym, is accessed for a write or read operation, all the pointers waym and newer, except for the MRU pointer, are promoted to point to a way pointed to by a newer neighboring pointer. The MRU pointer is changed to point to waym. For an invalidate operation in which one of the ways, wayk is invalidated, all the pointers pointing to wayk and older are demoted, except for the LRU pointer. The LRU pointer is pointed to the invalidated way.
摘要翻译：使用指向N路存储器块集合的各个方式的一组N个指针寄存器来实现最近最少使用（LRU）高速缓存替换算法。指针寄存器之一是LRU指针，指向最近最少使用的方式，另一个指针寄存器是最近使用的（MRU）指针，指向最近使用的方式。对于其中将新的存储器块写入N个路径中的一个的高速缓存填充操作，新的存储器块被写入由LRU指针指向的方式（wayn）。除了MRU指针之外的所有指针被提升以指向相应较新的相邻指针指向的方式，较新的相邻指针是朝向MRU指针的邻居。更新MRU指针以指向写入新内存块的方式。对于缓存命中，其中访问集合（waym）中的一个存储器块用于写入或读取操作，除了MRU指针之外，所有指向waym和更新的指针都被提升为指向一个较新的相邻指针 MRU指针更改为指向waym。对于无效操作，其中一种方式，wayk无效，除了LRU指针之外，所有指向wayk和old的指针都将被降级。 LRU指针指向无效的方式。

8. 发明申请

US20120023314A1 PAIRED EXECUTION SCHEDULING OF DEPENDENT MICRO-OPERATIONS 审中-公开
标题翻译：配对执行依赖性微操作
公开(公告)号：US20120023314A1
公开(公告)日：2012-01-26
申请号：US12840835
申请日：2010-07-21
申请人： Matthew M. Crum , Michael D. Achenbach , Betty A. McDaniel , Benjamin T. Sander
发明人： Matthew M. Crum , Michael D. Achenbach , Betty A. McDaniel , Benjamin T. Sander
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3838 , G06F9/3826
摘要： A method and mechanism for reducing latency of a multi-cycle scheduler within a processor. A processor comprises a front end pipeline that determines data dependencies between instructions prior to a scheduling pipe stage. For each data dependency, a distance value is determined based on a number of instructions a younger dependent instruction is located from a corresponding older (in program order) instruction. When the younger dependent instruction is allocated an entry in a multi-cycle scheduler, this distance value may be used to locate an entry storing the older instruction in the scheduler. When the older instruction is picked for issue, the younger dependent instruction is marked as pre-picked. In an immediately subsequent clock cycle, the younger dependent instruction may be picked for issue, thereby reducing the latency of the multi-cycle scheduler.
摘要翻译：一种用于减少处理器内的多周期调度器的等待时间的方法和机制。处理器包括前端流水线，其在调度管道级之前确定指令之间的数据依赖性。对于每个数据依赖性，基于较年轻的依赖指令从相应的较旧（在程序顺序）指令中定位的指令的数量来确定距离值。当在多循环调度器中分配较年轻的依赖指令时，该距离值可以用于定位存储在调度器中的旧指令的条目。当较老的指令被挑选出来时，年龄较大的指令被标记为预选。在随后的时钟周期中，可以挑选较年轻的依赖指令以进行发布，从而减少多周期调度器的等待时间。

9. 发明授权

US06950925B1 Scheduler for use in a microprocessor that supports data-speculative execution 有权
标题翻译：调度器用于支持数据推测执行的微处理器
公开(公告)号：US06950925B1
公开(公告)日：2005-09-27
申请号：US10229563
申请日：2002-08-28
申请人： Benjamin T. Sander , Mitchell Alsup , Michael Filippo
发明人： Benjamin T. Sander , Mitchell Alsup , Michael Filippo
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842
摘要： A microprocessor may include several execution units and a scheduler coupled to issue operations to at least one of the execution units. The scheduler may include several entries. A first entry may be allocated to a first operation. The first entry includes a source status indication for each of the first operation's operands. Each source status indication indicates whether a value of a respective one of the first operation's operands is speculative. The scheduler is configured to update one of the first entry's source status indications to indicate that a value of a respective one of the first operation's operands is non-speculative in response to receiving an indication that a value of a result of a second operation is non-speculative.
摘要翻译：微处理器可以包括若干个执行单元和一个调度器，它被耦合以向至少一个执行单元发出操作。调度器可以包括几个条目。可以将第一条目分配给第一操作。第一个条目包括每个第一个操作的操作数的源状态指示。每个源状态指示指示第一操作的操作数中的相应一个的值是否是推测性的。调度器被配置为响应于接收到第二操作的结果的值不是的指示，更新第一条目的源状态指示之一以指示第一操作的操作数中的相应一个的值是非推测性的特别的

10. 发明授权

US06725337B1 Method and system for speculatively invalidating lines in a cache 有权
标题翻译：在缓存中推测使无效行的方法和系统
公开(公告)号：US06725337B1
公开(公告)日：2004-04-20
申请号：US09859290
申请日：2001-05-16
申请人： Teik-Chung Tan , Benjamin T. Sander
发明人： Teik-Chung Tan , Benjamin T. Sander
IPC分类号： G06F1200
CPC分类号： G06F12/0891
摘要： A cache controller configured to speculatively invalidate a cache line may respond to an invalidating request or instruction immediately instead of waiting for error checking to complete. In case the error checking determines that the invalidation is erroneous and thus should not be performed, the cache controller protects the speculatively invalidated cache line from modification until error checking is complete. This way, if the invalidation is later found to be erroneous, the speculative invalidation can be reversed. If error checking completes without detecting any errors, the speculative invalidation becomes non-speculative.
摘要翻译：配置为推测无效高速缓存行的高速缓存控制器可以立即响应无效请求或指令，而不是等待错误检查完成。如果错误检查确定无效是错误的，因此不应该执行，则缓存控制器保护推测无效的高速缓存行不被修改，直到错误检查完成。这样，如果后来发现无效是错误的，则可以颠倒推测无效。如果错误检查完成而没有检测到任何错误，则推测无效将成为非投机性的。

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