专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070012983A1 Terminations for semiconductor devices with floating vertical series capacitive structures 审中-公开
标题翻译：具有浮动垂直串联电容结构的半导体器件的端接
公开(公告)号：US20070012983A1
公开(公告)日：2007-01-18
申请号：US11487142
申请日：2006-07-14
申请人： Robert Yang , Richard Blanchard , Francois Hebert
发明人： Robert Yang , Richard Blanchard , Francois Hebert
IPC分类号： H01L29/94
CPC分类号： H01L29/7803 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/4236 , H01L29/7802 , H01L29/7811 , H01L29/7813
摘要： This invention relates to achieving high breakdown voltage and low on-resistance in semiconductor devices that have top, intermediate and bottom regions with a controllable current path traversing any of these regions. The device has an insulating trench that is coextensive with the top and intermediate regions and girds these regions from at least one side and preferably from both or all sides. A series capacitive structure with a biased top element and a number of floating elements is disposed in the insulating trench, and the intermediate region is endowed with a capacitive property that is chosen to establish a capacitive interaction or coupling between the series capacitive structure and the intermediate region so that the breakdown voltage VBD is maximized and on-resistance is minimized. A second series capacitive structure disposed in a second insulating trench can be employed to terminate the device.
摘要翻译：本发明涉及在半导体器件中实现高击穿电压和低导通电阻，所述半导体器件具有穿过任何这些区域的可控电流路径的顶部区域，中间区域和底部区域。该装置具有与顶部和中间区域共同延伸的绝缘沟槽，并且从至少一个侧面，优选地从两侧或全部侧面将这些区域线化。具有偏置顶部元件和多个浮动元件的串联电容结构设置在绝缘沟槽中，并且中间区域具有被选择用于建立串联电容结构和中间体之间的电容性相互作用或耦合的电容性质区域，使得击穿电压V BAT最大化，导通电阻最小化。可以采用设置在第二绝缘沟槽中的第二串联电容结构来终止该器件。

2. 发明申请

US20070035906A1 Transient blocking unit 审中-公开
标题翻译：瞬态阻断单位
公开(公告)号：US20070035906A1
公开(公告)日：2007-02-15
申请号：US11503357
申请日：2006-08-10
申请人： Richard Harris , Richard Blanchard , Francois Hebert
发明人： Richard Harris , Richard Blanchard , Francois Hebert
IPC分类号： H02H9/06
CPC分类号： H02H9/025
摘要： Improved electrical transient blocking is provided with a transient blocking unit (TBU) having a partial disconnect capability. A TBU is an arrangement of voltage controlled switches that normally conducts, but switches to a disconnected state in response to an above-threshold input transient. Partial disconnection improves the power handling capability of a TBU by preventing thermal damage to the TBU. Partial TBU disconnection can be implemented to keep power dissipation in the TBU below a predetermined level Pmax, thereby avoiding thermal damage to the TBU by keeping the TBU temperature below a temperature limit Tmax. Alternatively, partial TBU disconnection can be implemented to keep TBU temperature below Tmax using direct temperature sensing and feedback.
摘要翻译：提供了具有部分断开能力的瞬态阻塞单元（TBU）的改进的电气瞬态阻塞。 TBU是通常导通的电压控制开关的布置，但是响应于高于阈值的输入瞬变而切换到断开状态。部分断开通过防止TBU的热损坏提高了TBU的功率处理能力。可以实施部分TBU断开以将TBU中的功率消耗降低到预定水平P max以下，从而通过将TBU温度保持在温度下限T max以下来避免对TBU的热损伤， SUB>。或者，可以使用直接温度感测和反馈来实现部分TBU断开以将TBU温度保持在T 以下。

3. 发明申请

US20060238936A1 Apparatus and method for transient blocking employing relays 审中-公开
标题翻译：采用继电器的瞬态阻塞装置和方法
公开(公告)号：US20060238936A1
公开(公告)日：2006-10-26
申请号：US11410575
申请日：2006-04-24
申请人： Richard Blanchard , Richard Harris , Francois Hebert
发明人： Richard Blanchard , Richard Harris , Francois Hebert
IPC分类号： H02H9/00
CPC分类号： H01J1/72 , C09K11/59 , H01H9/548 , H02H9/025
摘要： An apparatus and a method for uni-directional and bi-directional transient blocking. The uni-directional apparatus has a depletion mode n-channel device at its input and a normally closed relay, e.g., a micro-electro-mechanical (MEM) relay, interconnected with the depletion mode n-channel device and the input in such a way that at a predetermined current value the transient causes the normally closed relay to switch into an open state and apply a bias voltage Vn on the depletion mode n-channel device that is sufficiently high to switch it “off” thus block the transient. An analogous arrangement at the output taking advantage of the same or a second relay renders the apparatus bi-directional. The structure of the apparatus and the method of operation ensure a reliable and repeatable trip current Itrip and render the apparatus very robust and feasible for low-cost manufacture.
摘要翻译：一种用于单向和双向瞬态阻塞的装置和方法。单向设备在其输入端具有耗尽模式n沟道器件和常闭继电器，例如与耗尽型n沟道器件互连的微机电（MEM）继电器，以及在这种在预定电流值下，瞬态使常闭继电器切换到打开状态，并在足够高以切换它的耗尽型n沟道器件上施加偏置电压V N“ 关闭“从而阻止瞬态。利用相同或第二中继器在输出端处的类似布置使设备双向。该装置的结构和操作方法确保了可靠且可重复的跳闸电流跳闸，并且使得该装置非常坚固且可用于低成本制造。

4. 发明申请

US20060255401A1 Increasing breakdown voltage in semiconductor devices with vertical series capacitive structures 审中-公开
标题翻译：增加具有垂直串联电容结构的半导体器件中的击穿电压
公开(公告)号：US20060255401A1
公开(公告)日：2006-11-16
申请号：US11202523
申请日：2005-08-11
申请人： Robert Yang , Francois Hebert
发明人： Robert Yang , Francois Hebert
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7802 , H01L29/407 , H01L29/4236 , H01L29/7395 , H01L29/74 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L29/861
摘要： This invention relates to an apparatus and method for achieving high breakdown voltage and low on-resistance in semiconductor devices that have top, intermediate and bottom regions with a controllable current path traversing any of these regions. The device has an insulating trench that is coextensive with the top and intermediate regions and girds these regions from at least one side and preferably from both or all sides. A series capacitive structure with a biased top element and a number of floating elements is disposed in the insulating trench, and the intermediate region is endowed with a capacitive property that is chosen to establish a capacitive interaction or coupling between the series capacitive structure and the intermediate region so that the breakdown voltage VBD is maximized and on-resistance is minimized. The capacitive property of the intermediate region is established by an appropriately chosen material constitution and is further controlled by a predetermined constitution of the insulating trench. The apparatus and method of invention are useful in any number of semiconductor devices including, among other, transistors, bipolar transistors, MOSFETs, JFETs, thyristors and diodes.
摘要翻译：本发明涉及一种用于实现半导体器件中的高击穿电压和低导通电阻的装置和方法，所述半导体器件具有穿过任何这些区域的可控电流路径的顶部，中间和底部区域。该装置具有与顶部和中间区域共同延伸的绝缘沟槽，并且从至少一个侧面，优选地从两侧或全部侧面将这些区域线化。具有偏置顶部元件和多个浮动元件的串联电容结构设置在绝缘沟槽中，并且中间区域具有被选择用于建立串联电容结构和中间体之间的电容性相互作用或耦合的电容性质区域，使得击穿电压V BAT最大化，导通电阻最小化。通过适当选择的材料结构建立中间区域的电容性质，并通过绝缘沟槽的预定结构进一步控制。本发明的装置和方法可用于任何数量的半导体器件，其中包括晶体管，双极晶体管，MOSFET，JFET，晶闸管和二极管。

5. 发明授权

US09257525B2 Systems and methods for forming isolated devices in a handle wafer 有权
标题翻译：在处理晶片中形成隔离器件的系统和方法
公开(公告)号：US09257525B2
公开(公告)日：2016-02-09
申请号：US13283139
申请日：2011-10-27
申请人： I-Shan Sun , Rick Carlton Jerome , Francois Hebert
发明人： I-Shan Sun , Rick Carlton Jerome , Francois Hebert
IPC分类号： H01L21/00 , H01L29/66 , H01L23/48 , H01L23/535 , H01L21/74 , H01L27/06
CPC分类号： H01L29/66204 , H01L21/743 , H01L23/481 , H01L23/535 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the at least one trench, the electrically conductive material providing an electrical connection to the electrical device through the active layer.
摘要翻译：提供了一种通过积分硅通过集成的方法。该方法包括在处理晶片中形成电气装置。该方法还包括在手柄晶片和电气装置上形成隔离层，并将活性层连接到隔离层。此外，该方法包括通过有源层和隔离层形成至少一个沟槽，以暴露处理晶片的一部分并在至少一个沟槽中沉积导电材料，导电材料提供与电设备通过活动层。

6. 发明授权

US09209173B2 Single die output power stage using trench-gate low-side and LDMOS high-side MOSFETS, structure and method 有权
标题翻译：单晶片输出功率级采用沟槽栅极低边和LDMOS高边MOSFET，结构与方法
公开(公告)号：US09209173B2
公开(公告)日：2015-12-08
申请号：US13415384
申请日：2012-03-08
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/45 , H01L29/66 , H01L29/78 , H02M7/00
CPC分类号： H01L27/088 , H01L21/26513 , H01L21/823437 , H01L21/823487 , H01L23/535 , H01L23/62 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66712 , H01L29/66734 , H01L29/7802 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7816 , H01L29/7835 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/1461 , H01L2924/30107 , H01L2924/3025 , H02M7/003 , H01L2924/00
摘要： A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.
摘要翻译：电压转换器包括具有可以形成在单个管芯（“PowerDie”）上的高侧器件和低侧器件的输出电路。高侧器件可以包括横向扩散金属氧化物半导体（LDMOS），而低侧器件可以包括沟槽栅极垂直扩散金属氧化物半导体（VDMOS）。电压转换器还可以包括在不同管芯上的控制器电路，其可以电耦合到输出电路并与输出电路共同封装。

7. 发明申请

US20120098090A1 HIGH-EFFICIENCY POWER CONVERTERS WITH INTEGRATED CAPACITORS 审中-公开
标题翻译：具有集成电容器的高效功率转换器
公开(公告)号：US20120098090A1
公开(公告)日：2012-04-26
申请号：US13069789
申请日：2011-03-23
申请人： Francois Hebert , Shea Petricek , Nikhil Kelkar
发明人： Francois Hebert , Shea Petricek , Nikhil Kelkar
IPC分类号： H01L29/92 , H01L21/56
CPC分类号： H01L23/49589 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/16 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/0603 , H01L2224/16265 , H01L2224/371 , H01L2224/37147 , H01L2224/3718 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/48137 , H01L2224/48247 , H01L2224/48265 , H01L2224/4912 , H01L2224/49175 , H01L2224/73207 , H01L2224/73221 , H01L2924/00014 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01042 , H01L2924/01056 , H01L2924/01072 , H01L2924/01073 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1434 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/19106 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A power converter device comprises a substrate, a power die mounted on the substrate, and a capacitor die mounted over the power die in a stacked configuration. The capacitor die is electrically coupled to the power die. A packaging material encapsulates the power die and the capacitor die. An integrated circuit die can also be mounted to the substrate and electrically coupled to the power die to receive power signals from the power die, with the packaging material also encapsulating the integrated circuit die.
摘要翻译：功率转换器装置包括衬底，安装在衬底上的功率管芯和以堆叠构造安装在功率管芯上的电容器管芯。电容器管芯电耦合到功率管芯。封装材料封装了电源管芯和电容器管芯。集成电路管芯也可以安装到衬底上并且电耦合到功率管芯以从功率管芯接收功率信号，封装材料也封装集成电路管芯。

8. 发明申请

US20120007097A1 SCHOTTKY DIODE WITH COMBINED FIELD PLATE AND GUARD RING 审中-公开
标题翻译：肖特基二极管与组合的现场板和保护环
公开(公告)号：US20120007097A1
公开(公告)日：2012-01-12
申请号：US12944163
申请日：2010-11-11
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L29/20 , H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/2003 , H01L29/402 , H01L29/66143
摘要： A Schottky diode comprising a merged guard ring and field plate defining a Schottky contact region is provided. A Schottky metal is formed over at least partially over the Schottky contact region and at least partially over the merged guard ring and field plate.
摘要翻译：提供了包括合并的保护环和限定肖特基接触区域的场板的肖特基二极管。肖特基金属至少部分地形成在肖特基接触区域上并且至少部分地在合并的保护环和场板上形成。

9. 发明申请

US20110107589A1 PLANAR GROOVED POWER INDUCTOR STRUCTURE AND METHOD 有权
标题翻译：平面电力电力电感器结构与方法
公开(公告)号：US20110107589A1
公开(公告)日：2011-05-12
申请号：US13007551
申请日：2011-01-14
申请人： Francois Hebert , Tao Feng , Jun Lu
发明人： Francois Hebert , Tao Feng , Jun Lu
IPC分类号： H01F7/06
CPC分类号： H01F17/0033 , H01F1/344 , H01F41/046 , H01F2017/002 , Y10T29/4902
摘要： An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.
摘要翻译：电感器可以包括平面铁氧体磁芯。第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

10. 发明申请

US20090322461A1 PLANAR GROOVED POWER INDUCTOR STRUCTURE AND METHOD 有权
标题翻译：平面电力电力电感器结构与方法
公开(公告)号：US20090322461A1
公开(公告)日：2009-12-31
申请号：US12165423
申请日：2008-06-30
申请人： Francois Hebert , Tao Feng , Jun Lu
发明人： Francois Hebert , Tao Feng , Jun Lu
IPC分类号： H01F27/02
CPC分类号： H01F17/0033 , H01F1/344 , H01F41/046 , H01F2017/002 , Y10T29/4902
摘要： An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.
摘要翻译：电感器可以包括平面铁氧体磁芯。第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式