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1. 发明授权

US08258817B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08258817B2
公开(公告)日：2012-09-04
申请号：US12884623
申请日：2010-09-17
申请人： Ryo Fukuda , Masaru Koyanagi
发明人： Ryo Fukuda , Masaru Koyanagi
IPC分类号： H03K5/153
CPC分类号： H01L27/092 , H01L2924/0002 , H03F3/3028 , H03F3/45183 , H03F2200/411 , H03F2203/45511 , H01L2924/00
摘要： According to one embodiment, a semiconductor integrated circuit includes first to six transistors and a constant current source circuit. The first and second transistors form a current mirror circuit connected to a first power source node. The third and fourth transistors form a differential pair circuit. The third and fourth transistors receive first and second external signals at their gates, respectively. The constant current source circuit has one end connected to source terminals of the third and fourth transistors, and the other end connected to a second power source node. The fifth and sixth transistors form a current pathway between a common gate node of the first and second transistors and the constant current source circuit. The gate of fifth transistor is connected to a signal output node. The gate of sixth transistor receives a signal of logic opposite to a signal to be obtained at the signal output node.
摘要翻译：根据一个实施例，半导体集成电路包括第一至六个晶体管和恒流源电路。第一和第二晶体管形成连接到第一电源节点的电流镜电路。第三和第四晶体管形成差分对电路。第三和第四晶体管分别在其栅极处接收第一和第二外部信号。恒流源电路的一端连接到第三和第四晶体管的源极端子，另一端连接到第二电源节点。第五和第六晶体管在第一和第二晶体管的公共栅极节点与恒流源电路之间形成电流通路。第五晶体管的栅极连接到信号输出节点。第六晶体管的栅极接收与在信号输出节点处获得的信号相反的逻辑信号。

2. 发明申请

US20110133791A1 OUTPUT BUFFER CIRCUIT, INPUT BUFFER CIRCUIT, AND INPUT/OUTPUT BUFFER CIRCUIT 有权
标题翻译：输出缓冲电路，输入缓冲电路和输入/输出缓冲电路
公开(公告)号：US20110133791A1
公开(公告)日：2011-06-09
申请号：US12963114
申请日：2010-12-08
申请人： Masaru Koyanagi , Yasufumi Kajiyama , Ryo Fukuda , Fumiyoshi Matsuoka , Yasuhiro Suematsu
发明人： Masaru Koyanagi , Yasufumi Kajiyama , Ryo Fukuda , Fumiyoshi Matsuoka , Yasuhiro Suematsu
IPC分类号： H03K3/01
CPC分类号： H03K19/00384 , H03K19/01721
摘要： An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.
摘要翻译：根据实施例的输出缓冲器电路包括多个缓冲电路，每个缓冲电路包括一个晶体管，用于响应于输入信号的变化而改变输出端的输出信号，该输出缓冲电路被配置以使得能够选择性地驱动多个缓冲电路。多个缓冲电路中的每一个包括多个输出晶体管，其具有在提供一定固定电压的固定电压端子和输出端子之间彼此并联形成的各自的电流路径，并且根据控制信号由外部提供。包含在多个缓冲电路的每一个中的多个输出晶体管形成为具有一定的尺寸比。

3. 发明授权

US08405432B2 Output buffer circuit, input buffer circuit, and input/output buffer circuit 有权
标题翻译：输出缓冲电路，输入缓冲电路，输入/输出缓冲电路
公开(公告)号：US08405432B2
公开(公告)日：2013-03-26
申请号：US12963114
申请日：2010-12-08
申请人： Masaru Koyanagi , Yasufumi Kajiyama , Ryo Fukuda , Fumiyoshi Matsuoka , Yasuhiro Suematsu
发明人： Masaru Koyanagi , Yasufumi Kajiyama , Ryo Fukuda , Fumiyoshi Matsuoka , Yasuhiro Suematsu
IPC分类号： H03K3/01
CPC分类号： H03K19/00384 , H03K19/01721
摘要： An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.
摘要翻译：根据实施例的输出缓冲器电路包括多个缓冲电路，每个缓冲电路包括一个晶体管，用于响应于输入信号的变化而改变输出端的输出信号，该输出缓冲电路被配置以使得能够选择性地驱动多个缓冲电路。多个缓冲电路中的每一个包括多个输出晶体管，其具有在提供一定固定电压的固定电压端子和输出端子之间彼此并联形成的各自的电流路径，并且根据控制信号由外部提供。包含在多个缓冲电路的每一个中的多个输出晶体管形成为具有一定的尺寸比。

4. 发明申请

US20110128063A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20110128063A1
公开(公告)日：2011-06-02
申请号：US12884533
申请日：2010-09-17
申请人： Ryo Fukuda , Masaru Koyanagi
发明人： Ryo Fukuda , Masaru Koyanagi
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.
摘要翻译：根据一个实施例，半导体集成电路包括第一和第二电平移位电路。第一电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，第二电源系统的第一信号和第一信号的电平反转信号被输入到该第一电源系统。第二电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，并且第二电源系统的第一信号的电平反转信号和第一电平系统的输出信号移位器被输入。第一和第二电平移位器具有基本上相同的电路配置，并且第一和第二电平移位器中对应的晶体管的驱动能力基本上相等。

5. 发明授权

US08558602B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08558602B2
公开(公告)日：2013-10-15
申请号：US12884533
申请日：2010-09-17
申请人： Ryo Fukuda , Masaru Koyanagi
发明人： Ryo Fukuda , Masaru Koyanagi
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.
摘要翻译：根据一个实施例，半导体集成电路包括第一和第二电平移位电路。第一电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，第二电源系统的第一信号和第一信号的电平反转信号被输入到该第一电源系统。第二电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，并且第二电源系统的第一信号的电平反转信号和第一电平系统的输出信号移位器被输入。第一和第二电平移位器具有基本上相同的电路配置，并且第一和第二电平移位器中对应的晶体管的驱动能力基本上相等。

6. 发明授权

US08405428B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08405428B2
公开(公告)日：2013-03-26
申请号：US13098752
申请日：2011-05-02
申请人： Ryo Fukuda , Masaru Koyanagi
发明人： Ryo Fukuda , Masaru Koyanagi
IPC分类号： H03K5/153
CPC分类号： H03K17/04 , H03K19/018521
摘要： A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.
摘要翻译：恒流源电路包括连接到第二节点的一端作为第三和第四晶体管的源极，另一端连接到提供不同于第一电压的第二电压的第二电源节点。钳位电路被配置为在第二节点和第二电源节点之间形成电流路径。当第一外部输入信号从第一状态切换到第二状态时，它将第二节点的电位调整到一定的电位。

7. 发明申请

US20120068256A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120068256A1
公开(公告)日：2012-03-22
申请号：US13232492
申请日：2011-09-14
申请人： Ryo Fukuda , Yoshihisa Iwata
发明人： Ryo Fukuda , Yoshihisa Iwata
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11578 , G11C16/0416 , H01L27/11565 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.
摘要翻译：在半导体衬底上方形成绝缘膜。第一导电层形成在电介质膜中并沿第一方向延伸。第一导电层连接到第一选择晶体管。形成在电介质膜中并沿第一方向延伸的第二导电层。第二导电层连接到第二选择晶体管。半导体层连接到第一和第二导电层两者并用作存储晶体管的沟道层。在半导体层上形成栅极绝缘膜。栅极绝缘膜包括作为其一部分的电荷累积膜。第三导电层被栅极绝缘膜包围。

8. 发明授权

US07958279B2 Asynchronous serial data apparatus for transferring data between one transmitter and a plurality of shift registers, avoiding skew during transmission 失效
标题翻译：用于在一个发射机和多个移位寄存器之间传送数据的异步串行数据装置，避免传输期间的偏斜
公开(公告)号：US07958279B2
公开(公告)日：2011-06-07
申请号：US12405953
申请日：2009-03-17
申请人： Tomohisa Takai , Ryo Fukuda
发明人： Tomohisa Takai , Ryo Fukuda
IPC分类号： G06F13/00 , G06F13/12
CPC分类号： G06F13/4282
摘要： A semiconductor integrated circuit apparatus, comprising a data transmitter circuit, and a plurality of data receiver circuits each having a data converter circuit which restores each of bits of identification number data and transfer data from a shift register of the data transmitter circuit to 2-bit complementary data transmitted via first and second transmission lines, a reception control circuit which, when a transfer completion signal has been received via a third transmission line, compares an allocated identification number with the restored identification number data, and a shift register provided in association with the reception control circuit, wherein each reception control circuit feeds transfer data transmitted from the data transmitter circuit corresponding to the identification number data to the associated shift register in accordance with a result of comparison between the identification number data and the allocated identification number.
摘要翻译：一种半导体集成电路装置，包括数据发送器电路和多个数据接收器电路，每个数据接收器电路具有数据转换器电路，其恢复识别号码数据的每一位并将数据从数据发送器电路的移位寄存器传送到2位通过第一和第二传输线传输的补充数据;接收控制电路，当经由第三传输线接收到传送完成信号时，将分配的识别号与恢复的标识号数据进行比较，以及移位寄存器接收控制电路，其中每个接收控制电路根据识别号码数据和所分配的识别号码之间的比较结果，将对应于识别号码数据的数据发送器电路发送的传送数据提供给相关联的移位寄存器。

9. 发明授权

US07609551B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07609551B2
公开(公告)日：2009-10-27
申请号：US11860956
申请日：2007-09-25
申请人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： H01L29/792 , G11C11/404 , G11C11/4074 , G11C14/0018 , G11C2211/4016 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42344 , H01L29/785 , H01L29/78648
摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.
摘要翻译：本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。

10. 发明授权

US07602657B2 Semiconductor memory device having floating body cell 失效
标题翻译：具有浮体电池的半导体存储器件
公开(公告)号：US07602657B2
公开(公告)日：2009-10-13
申请号：US11950097
申请日：2007-12-04
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C7/065 , G11C7/08 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/2281 , G11C2211/4016
摘要： A semiconductor memory device includes a sense amplifier for the FBC, a first node and a second node can be disconnected from each other by a first isolation transistor. A third node and a fourth node can be disconnected from each other by a second isolation transistor. The first node is connected to the first memory cell. The third node is connected to the second memory cell. A first amplification transistor and a second amplification transistor are connected between the first node and the third node. A third amplification transistor and a fourth amplification transistor are connected between the second node and the fourth node. This enables to parallelly execute read data transfer to the data lines and precharge to prepare for the next read operation.
摘要翻译：半导体存储器件包括用于FBC的读出放大器，第一节点和第二节点可以通过第一隔离晶体管彼此断开。第三节点和第四节点可以通过第二隔离晶体管彼此断开。第一个节点连接到第一个存储单元。第三节点连接到第二个存储单元。第一放大晶体管和第二放大晶体管连接在第一节点和第三节点之间。第三放大晶体管和第四放大晶体管连接在第二节点和第四节点之间。这使得能够并行地执行对数据线的读取数据传输并预充电以准备下一次读取操作。

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