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1. 发明授权

US07609551B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07609551B2
公开(公告)日：2009-10-27
申请号：US11860956
申请日：2007-09-25
申请人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： H01L29/792 , G11C11/404 , G11C11/4074 , G11C14/0018 , G11C2211/4016 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42344 , H01L29/785 , H01L29/78648
摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.
摘要翻译：本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。

2. 发明申请

US20080237695A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20080237695A1
公开(公告)日：2008-10-02
申请号：US11860956
申请日：2007-09-25
申请人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C11/404 , G11C11/4074 , G11C14/0018 , G11C2211/4016 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42344 , H01L29/785 , H01L29/78648
摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.
摘要翻译：本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。

3. 发明授权

US07692963B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07692963B2
公开(公告)日：2010-04-06
申请号：US11934337
申请日：2007-11-02
申请人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C11/4099 , G11C2211/4016 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.
摘要翻译：本公开涉及包括半导体层的半导体存储器件; 与所述半导体层的第一表面接触的电荷陷阱膜; 与所述半导体层的第二表面接触的栅极绝缘膜，所述第二表面与所述第一表面相对; 与电荷陷阱膜接触的背栅电极; 与栅极绝缘膜接触的栅电极; 在半导体层中形成的源极和漏极; 以及设置在所述漏极和源极之间的体区，所述体区域处于电浮置状态，其中通过改变数量来调整包括所述源极，漏极和所述栅电极的存储单元的阈值电压或漏极电流的多数载体积聚在身体区域中，并且一定量的电荷被捕获到电荷陷阱膜中。

4. 发明申请

US20080239789A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20080239789A1
公开(公告)日：2008-10-02
申请号：US11934337
申请日：2007-11-02
申请人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C11/24 , H01L27/108 , G11C11/34
CPC分类号： G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C11/4099 , G11C2211/4016 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.
摘要翻译：本公开涉及包括半导体层的半导体存储器件; 与所述半导体层的第一表面接触的电荷陷阱膜; 与所述半导体层的第二表面接触的栅极绝缘膜，所述第二表面与所述第一表面相对; 与电荷陷阱膜接触的背栅电极; 与栅极绝缘膜接触的栅电极; 在半导体层中形成的源极和漏极; 以及设置在所述漏极和源极之间的体区，所述体区域处于电浮置状态，其中通过改变数量来调整包括所述源极，漏极和所述栅电极的存储单元的阈值电压或漏极电流的多数载体积聚在身体区域中，并且一定量的电荷被捕获到电荷陷阱膜中。

5. 发明授权

US07977738B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07977738B2
公开(公告)日：2011-07-12
申请号：US12497010
申请日：2009-07-02
申请人： Yoshihiro Minami , Takashi Ohsawa , Tomoaki Shino , Takeshi Hamamoto , Akihiro Nitayama
发明人： Yoshihiro Minami , Takashi Ohsawa , Tomoaki Shino , Takeshi Hamamoto , Akihiro Nitayama
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/1022 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.
摘要翻译：半导体存储器件包括电漂浮体; 来源下水道栅电极，其每一个经由栅极电介质膜与所述一个主体的一个侧表面相邻; 板，其每一个经由板电介质膜与所述一个主体的另一侧表面相邻; 排水口上的第一位线，第一位线包括具有与排水管相同的导电类型的半导体; 和在第一位线的半导体上的发射极，发射器包括与第一位线的半导体的导电类型相反的导电类型的半导体，其中发射体堆叠在主体和漏极之上。

6. 发明申请

US20100019304A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100019304A1
公开(公告)日：2010-01-28
申请号：US12497010
申请日：2009-07-02
申请人： Yoshihiro MINAMI , Takashi Ohsawa , Tomoaki Shino , Takeshi Hamamoto , Akihiro Nitayama
发明人： Yoshihiro MINAMI , Takashi Ohsawa , Tomoaki Shino , Takeshi Hamamoto , Akihiro Nitayama
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L27/1022 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.
摘要翻译：半导体存储器件包括电漂浮体; 来源下水道栅电极，其每一个经由栅极电介质膜与所述一个主体的一个侧表面相邻; 板，其每一个经由板电介质膜与所述一个主体的另一侧表面相邻; 排水口上的第一位线，第一位线包括与排水管相同导电类型的半导体; 和在第一位线的半导体上的发射极，发射器包括与第一位线的半导体的导电类型相反的导电类型的半导体，其中发射体堆叠在主体和漏极之上。

7. 发明申请

US20080251830A1 SEMICONDUCTOR STORAGE DEVICE AND DRIVING METHOD THEREOF 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20080251830A1
公开(公告)日：2008-10-16
申请号：US12060522
申请日：2008-04-01
申请人： Tomoki Higashi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoki Higashi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： H01L27/102 , G11C16/04
CPC分类号： H01L27/1022 , G11C11/4023 , G11C11/4026 , G11C11/405 , G11C11/4085 , G11C2211/4016 , H01L21/8249 , H01L21/84 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.
摘要翻译：本公开涉及一种半导体存储装置，其包括设置在设置在半导体衬底上的绝缘层上的半导体层; 设置在所述半导体层中的源极层和漏极层; 设置在所述源极层和所述漏极层之间的主体，所述主体处于电浮动状态; 与源极层接触的发射极层，发射极层与源极层具有相反的导电类型; 包括源层，漏极层和主体的字线，字线被提供给在多个维度上排列的存储单元中沿第一方向排列的存储单元; 连接到沿着第一方向排列的存储单元的源层的源极线; 以及连接到沿与第一方向相交的第二方向排列的存储单元的漏极层的位线。

8. 发明授权

US07852696B2 Semiconductor memory device and driving method thereof 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07852696B2
公开(公告)日：2010-12-14
申请号：US12243195
申请日：2008-10-01
申请人： Takashi Ohsawa , Ryo Fukuda
发明人： Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C8/08 , G11C11/406 , G11C2211/4016 , G11C2211/4065
摘要： This disclosure concerns a memory including a memory cell including a drain, a source and a floating body, wherein when a refresh operation is executed, a first current is carried from the drain or the source to the body and a second current is carried from the body to the second gate electrode by applying a first voltage and a second voltage to the first gate electrode and the second gate electrode, the first voltage and the second voltage being opposite in polarity to each other, and a state of the memory cell is covered to an stationary state in which an amount of the electric charges based on the first current flowing in one cycle of the refresh operation is almost equal to an amount of the electric charges based on the second current flowing in one cycle of the refresh operation.
摘要翻译：本公开涉及包括包括漏极，源极和浮体的存储单元的存储器，其中当执行刷新操作时，第一电流从漏极或源被传送到主体，并且第二电流从通过向第一栅电极和第二栅电极施加第一电压和第二电压，第一电压和第二电压彼此极性相反，并且覆盖存储器单元的状态到第二栅极电极达到静止状态，其中基于在刷新操作的一个周期中流动的第一电流的电荷的量几乎等于基于在刷新操作的一个周期中流动的第二电流的电荷量。

9. 发明授权

US07893478B2 Semiconductor storage device and driving method thereof 失效
标题翻译：半导体存储装置及其驱动方法
公开(公告)号：US07893478B2
公开(公告)日：2011-02-22
申请号：US12060522
申请日：2008-04-01
申请人： Tomoki Higashi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoki Higashi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： H01L27/108 , H01L29/94 , H01L23/52 , H01L21/70 , H01L29/66
CPC分类号： H01L27/1022 , G11C11/4023 , G11C11/4026 , G11C11/405 , G11C11/4085 , G11C2211/4016 , H01L21/8249 , H01L21/84 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.
摘要翻译：本公开涉及一种半导体存储装置，其包括设置在设置在半导体衬底上的绝缘层上的半导体层; 设置在所述半导体层中的源极层和漏极层; 设置在所述源极层和所述漏极层之间的主体，所述主体处于电浮动状态; 与源极层接触的发射极层，发射极层与源极层具有相反的导电类型; 包括源层，漏极层和主体的字线，字线被提供给在多个维度上排列的存储单元中沿第一方向排列的存储单元; 连接到沿着第一方向排列的存储单元的源层的源极线; 以及连接到沿与第一方向相交的第二方向排列的存储单元的漏极层的位线。

10. 发明授权

US09608526B2 DC/DC converter, on-board unit and charging device 有权
公开(公告)号：US09608526B2
公开(公告)日：2017-03-28
申请号：US14371682
申请日：2012-04-27
申请人： Susumu Okura , Takashi Ohsawa
发明人： Susumu Okura , Takashi Ohsawa
IPC分类号： H02M3/335 , B60Q1/30 , B60L11/18 , H02J5/00
CPC分类号： H02M3/33507 , B60L11/1811 , B60L2210/10 , B60Q1/30 , H02J5/005 , H02J7/025 , H02J50/12 , H02M3/33576
摘要： A DC/DC converter 1 is configured to allow separation of a primary side constitution unit 3 and a secondary side constitution unit 4 of a transformer 2. A secondary side switching element FET 2 is provided in the secondary side constitution unit 4, and controls power supply to a load 12 by intermitting an output of a secondary winding L2. The primary side constitution unit 3 detects an electrical behavior of the primary side generated by the intermittent operation of the secondary side, and controls the power supplied from the primary winding L1 to the secondary winding L2 by operating the intermittent operation of the primary side switching element FET 1 such that a cycle or duty of the intermittent operation of the secondary side falls within a predetermined range.

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