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1. 发明授权

US11037629B2 Semiconductor memory device and method for operating thereof 有权
公开(公告)号：US11037629B2
公开(公告)日：2021-06-15
申请号：US16728363
申请日：2019-12-27
申请人： SK hynix Inc.
发明人： Jung Mi Ko , Kwang Ho Baek , Seong Je Park , Young Don Jung , Ji Hwan Kim , Jung Hwan Lee
IPC分类号： G11C16/08 , G11C16/10 , G11C16/26 , G11C16/34 , G11C16/04
摘要： Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.

2. 发明授权

US10971234B2 Page buffer, a memory device having page buffer, and a method of operating the memory device 有权
公开(公告)号：US10971234B2
公开(公告)日：2021-04-06
申请号：US16670764
申请日：2019-10-31
申请人： SK hynix Inc.
发明人： Jung Hwan Lee , Jung Mi Ko , Ji Hwan Kim , Kwang Ho Baek , Young Don Jung
IPC分类号： G11C16/24 , G11C16/34 , G11C16/30 , G11C16/10 , G11C16/08 , G11C11/56 , G11C16/04
摘要： Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.

3. 发明授权

US10790011B2 Address and command generation circuit, and semiconductor system 有权
公开(公告)号：US10790011B2
公开(公告)日：2020-09-29
申请号：US16122075
申请日：2018-09-05
申请人： SK hynix Inc.
发明人： Dong Uk Lee , Ji Hwan Kim , Heat Bit Park
IPC分类号： G11C11/00 , G11C11/4096 , G11C29/42 , G11C7/10 , G11C8/18 , G11C8/00 , G06F3/06
摘要： An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.

4. 发明授权

US09036429B2 Nonvolatile memory device and operating method thereof 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US09036429B2
公开(公告)日：2015-05-19
申请号：US13713505
申请日：2012-12-13
申请人： SK hynix Inc.
发明人： Beom Seok Hah , Jung Hwan Lee , Ji Hwan Kim , Myung Cho
IPC分类号： G11C5/14 , G11C7/00 , G11C29/46 , G11C29/16
CPC分类号： G11C7/00 , G11C29/16 , G11C29/46
摘要： A nonvolatile memory device including a memory cell arranged at a region where a word line and a bit line cross each other; a control signal generator configured to be enabled while the nonvolatile memory device operates in a test mode, and generate control signals which are not provided from an external device, based on a reference signal provided from the external device; and a control logic configured to control an operation for the memory cell according to the generated control signals.
摘要翻译：一种非易失性存储器件，包括布置在字线和位线彼此交叉的区域处的存储单元; 控制信号发生器，被配置为在所述非易失性存储器件在测试模式下工作时被使能，并且基于从所述外部设备提供的参考信号产生不从外部设备提供的控制信号; 以及控制逻辑，被配置为根据所生成的控制信号来控制对存储器单元的操作。

5. 发明授权

US10998053B2 Memory device and operating method thereof for applying a channel precharge voltage to bit lines after a sensing operation 有权
公开(公告)号：US10998053B2
公开(公告)日：2021-05-04
申请号：US16676157
申请日：2019-11-06
申请人： SK hynix Inc.
发明人： Jung Hwan Lee , Jung Mi Ko , Ji Hwan Kim , Kwang Ho Baek , Young Don Jung
IPC分类号： G11C7/12 , G11C16/24 , G11C16/04 , G11C16/34 , G11C16/26 , G11C16/30 , G11C16/08 , G11C16/16 , G11C8/08
摘要： A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.

6. 发明授权

US10818360B2 Memory device, memory system including the memory device 有权
公开(公告)号：US10818360B2
公开(公告)日：2020-10-27
申请号：US16445932
申请日：2019-06-19
申请人： SK hynix Inc.
发明人： Jong Hoon Lee , Ji Hwan Kim , Kwang Ho Baek , Jin Haeng Lee
IPC分类号： G11C16/10 , G11C16/30 , G11C16/34 , G06F3/06 , G11C16/24 , G11C16/04
摘要： The present disclosure relates to a memory device and a memory system including the same. The memory device includes a memory cell storing data, a voltage generation circuit selectively outputting a program voltage and verify voltages in response to an operation control signal, a page buffer including first latches and second latches, and storing first data sensed by a first sensing current in the first latches and second data sensed by a sensing current greater than the first sensing current in the second latches during a verify operation using the verify voltages, and a pass/fail check circuit determining a pass or fail of the verify operation of the memory cell according to the first data and allowable bits.

7. 发明授权

US09829537B2 Stack type semiconductor apparatus and system including the stack type semiconductor apparatus 有权
公开(公告)号：US09829537B2
公开(公告)日：2017-11-28
申请号：US15152741
申请日：2016-05-12
申请人： SK hynix Inc.
发明人： Ji Hwan Kim , Jong Chern Lee
IPC分类号： G11C29/00 , G01R31/317 , G01R31/3177 , H01L25/065 , H01L27/112
CPC分类号： G01R31/31723 , G01R31/3177 , G01R31/318513 , G01R31/318538 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L27/11206 , H01L2224/13025 , H01L2224/16146 , H01L2224/17181 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2225/06596
摘要： A stack type semiconductor apparatus may be provided. The stack type semiconductor apparatus may include a plurality of semiconductor chips stacked and configured for transferring signals through through-hole vias. Each of the plurality of stacked semiconductor chips may include an error detection circuit configured to perform a down scan for transferring a signal to a lower direction and an up scan for transferring a signal to an upper direction through through-hole vias in a column direction among the through-hole vias, and to determine whether the through-hole vias have failed according to a down scan result value and an up scan result value.

8. 发明授权

US09741786B2 Semiconductor integrated circuit device having with a reservoir capacitor 有权
公开(公告)号：US09741786B2
公开(公告)日：2017-08-22
申请号：US15054336
申请日：2016-02-26
申请人： SK hynix Inc.
发明人： Ji Hwan Kim
IPC分类号： H01L23/48 , H01L49/02 , H01L23/528 , H01L27/105
CPC分类号： H01L28/60 , H01L23/481 , H01L23/5286 , H01L27/105
摘要： A semiconductor integrated circuit device may include a through silicon via (TSV), a keep out zone and a plurality of dummy patterns. The TSV may be arranged in a selection region of a semiconductor substrate. The keep out zone may be configured to define a peripheral region of the TSV. The dummy patterns may be arranged in the keep out zone to receive a conductive signal. The dummy patterns may function as an electrode of a reservoir capacitor.

9. 发明授权

US11373699B2 Address and command generation circuit, and semiconductor system 有权
公开(公告)号：US11373699B2
公开(公告)日：2022-06-28
申请号：US17000052
申请日：2020-08-21
申请人： SK hynix Inc.
发明人： Dong Uk Lee , Ji Hwan Kim , Heat Bit Park
IPC分类号： G11C29/00 , G11C11/4096 , G11C29/42 , G11C7/10 , G11C8/18 , G11C8/00 , G06F3/06
摘要： An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.

10. 发明授权

US09331877B2 Receiver of semiconductor apparatus and semiconductor system including the same 有权
标题翻译：包括其的半导体装置和半导体系统的接收器
公开(公告)号：US09331877B2
公开(公告)日：2016-05-03
申请号：US14329533
申请日：2014-07-11
申请人： SK hynix Inc.
发明人： Ji Hwan Kim
IPC分类号： G11C7/10 , H04L27/06 , H04B1/24
CPC分类号： H04L27/06 , G11C7/1084 , H04B1/24
摘要： A receiver of a semiconductor apparatus includes a first buffer unit configured to buffer a first positive input signal and a first negative input signal having a phase opposite the phase of the first positive input signal and to output the buffered first positive input signal as a first positive transmission signal and to output the buffered first negative input signal as a first negative transmission signal in response to a first enable signal, a second buffer unit configured to buffer a second positive input signal and a second negative input signal having a phase opposite the phase of the second positive input signal and to output the buffered second positive input signal as a second positive transmission signal and to output the buffered second negative input signal as a second negative transmission signal in response to a second enable signal, is and an output unit configured to invert one of the first and second positive transmission signals and to output the inverted one of the first and second positive transmission signals as a positive output signal, and to invert one of the first and second negative transmission signals and to output the inverted one of the first and second negative transmission signals as a negative output signal.
摘要翻译：半导体装置的接收器包括：第一缓冲单元，被配置为缓冲第一正输入信号;以及第一负输入信号，具有与第一正输入信号的相位相反的相位，并输出缓冲的第一正输入信号作为第一正值并且响应于第一使能信号而输出缓冲的第一负输入信号作为第一负传输信号;第二缓冲单元，被配置为缓冲第二正输入信号;以及第二负输入信号，其具有与相位相反的相位第二正输入信号并输出缓冲的第二正输入信号作为第二正传输信号，并且响应于第二使能信号输出缓冲的第二负输入信号作为第二负传输信号，并且输出单元被配置为反转第一和第二正传输信号中的一个，并输出倒相的一个第一和第二正传输信号作为正输出信号，并且反转第一和第二负传输信号中的一个，并输出第一和第二负传输信号中的反相的一个作为负输出信号。

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