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1. 发明授权

US11636898B2 Semiconductor memory device and method for operating thereof 有权
公开(公告)号：US11636898B2
公开(公告)日：2023-04-25
申请号：US17337936
申请日：2021-06-03
申请人： SK hynix Inc.
发明人： Jung Mi Ko , Kwang Ho Baek , Seong Je Park , Young Don Jung , Ji Hwan Kim , Jung Hwan Lee
IPC分类号： G11C16/16 , G11C16/10 , G11C16/26 , G11C16/34 , G11C16/08 , G11C16/04
摘要： Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.

2. 发明授权

US10937513B2 Semiconductor memory device and operating method thereof 有权
公开(公告)号：US10937513B2
公开(公告)日：2021-03-02
申请号：US16667760
申请日：2019-10-29
申请人： SK hynix Inc.
发明人： Jung Mi Ko , Kwang Ho Baek , Ji Hwan Kim , Seong Je Park , Sung Hoon Ahn , Young Don Jung
IPC分类号： G11C16/34 , H01L27/11556 , H01L27/11582 , G11C16/10 , G11C16/04 , G11C11/56
摘要： A semiconductor memory device operates by applying a program pulse to a selected word line, updating a program pulse count value, determining a current sensing mode based upon the program pulse count value, and performing a program verify operation based upon the current sensing mode. The current sensing mode is determined by determining one of an individual state current sensing operation for determining verify pass or fail for one target program state and an all-state current sensing operation for determining verify pass or fail for all target program states.

3. 发明授权

US09123396B2 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US09123396B2
公开(公告)日：2015-09-01
申请号：US13960398
申请日：2013-08-06
申请人： SK HYNIX INC.
发明人： Chang Man Son , Chang Hyuk Lee , Go Hyun Lee , Kwang Ho Baek
IPC分类号： G11C5/06 , G11C8/10
CPC分类号： G11C8/10 , G11C7/18 , H01L27/11519 , H01L27/11524
摘要： A semiconductor device may include first conductive patterns coupled to a common source and selection lines of a memory block formed at a substrate, second conductive patterns configured to form a bit line coupled to the memory block, and third conductive patterns configured to transmit a block selection signal to couple local lines of the memory block to global lines. The first to third conductive patterns are arranged in different layers over the memory block.
摘要翻译：半导体器件可以包括耦合到公共源的第一导电图案和形成在衬底上的存储器块的选择线，配置成形成耦合到存储器块的位线的第二导电图案，以及被配置为发送块选择的第三导电图案信号将内存块的本地线路耦合到全局线路。第一至第三导电图案以不同的层布置在存储器块上。

4. 发明授权

US08913453B2 Semiconductor device and method of operating the same 有权
标题翻译：半导体装置及其操作方法
公开(公告)号：US08913453B2
公开(公告)日：2014-12-16
申请号：US13804490
申请日：2013-03-14
申请人： SK Hynix Inc.
发明人： Kwang Ho Baek , Jin Su Park
IPC分类号： G11C7/00 , G11C16/26
CPC分类号： G11C16/26
摘要： A semiconductor device including a memory block, which includes memory cells coupled to bit lines. The semiconductor device further includes a first sensing circuit coupled to an even bit line and configured to sense current flow through the even bit line in response to an even bit line control signal and an even discharge signal. The semiconductor device further includes a second sensing circuit coupled to an odd bit line and configured to sense current flow through the odd bit lines in response to an odd bit line control signal and an odd discharge signal. The first sensing circuit and second sensing circuit are configured to supply a ground voltage to the odd bit line when sensing the current flow through the even bit line, and to supply the ground voltage to the even bit line when sensing the current flow through the odd bit line.
摘要翻译：一种包括存储器块的半导体器件，其包括耦合到位线的存储器单元。半导体器件还包括耦合到偶数位线并被配置为响应于偶数位线控制信号和偶数放电信号来感测通过偶数位线的电流的第一感测电路。该半导体器件还包括耦合到奇数位线的第二感测电路，其被配置成响应于奇数位线控制信号和奇数放电信号而感测通过奇数位线的电流。第一感测电路和第二感测电路被配置为当感测通过偶数位线的电流时向奇数位线提供接地电压，并且当感测到通过奇数的电流时，将接地电压提供给偶位线位线。

5. 发明申请

US20140153340A1 METHOD FOR ERASING CHARGE TRAP DEVICES 有权
标题翻译：用于擦除电荷捕获装置的方法
公开(公告)号：US20140153340A1
公开(公告)日：2014-06-05
申请号：US13777930
申请日：2013-02-26
申请人： SK HYNIX INC.
发明人： Kwang Ho Baek
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C11/5635 , G11C16/14 , G11C16/3445
摘要： A method of erasing charge trap devices includes applying a first erase voltage to the charge trap devices; applying an erase verify voltage to the charge trap devices; performing a current first fail bit check operation including comparing a first number of charge trap devices, which are determined to be an erase fail based on the erase verify voltage, to a first reference value and determining a pass or fail based on the comparison result; when the current first fail bit check operation is determined to be a fail, determining whether a previous first fail bit check operation performed during a previous erase loop was passed or not; and when the previous first fail bit check operation performed during the previous erase loop was passed, setting a third erase voltage to a same level as a second erase voltage used during the previous erase loop.
摘要翻译：擦除电荷陷阱器件的方法包括：将第一擦除电压施加到电荷俘获器件; 向所述电荷陷阱装置施加擦除验证电压; 执行当前的第一故障位检查操作，其包括将基于擦除验证电压确定为擦除故障的第一数量的电荷陷阱器件与第一参考值进行比较，并且基于所述比较结果确定通过或失败; 当确定当前的第一故障位检查操作是否失败时，确定先前的擦除循环中执行的先前的第一故障位检查操作是否通过; 并且当在先前擦除循环期间执行的先前的第一个故障位检查操作被通过时，将第三擦除电压设置为与在先前擦除循环期间使用的第二擦除电压相同的电平。

6. 发明授权

US11037629B2 Semiconductor memory device and method for operating thereof 有权
公开(公告)号：US11037629B2
公开(公告)日：2021-06-15
申请号：US16728363
申请日：2019-12-27
申请人： SK hynix Inc.
发明人： Jung Mi Ko , Kwang Ho Baek , Seong Je Park , Young Don Jung , Ji Hwan Kim , Jung Hwan Lee
IPC分类号： G11C16/08 , G11C16/10 , G11C16/26 , G11C16/34 , G11C16/04
摘要： Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.

7. 发明授权

US10971234B2 Page buffer, a memory device having page buffer, and a method of operating the memory device 有权
公开(公告)号：US10971234B2
公开(公告)日：2021-04-06
申请号：US16670764
申请日：2019-10-31
申请人： SK hynix Inc.
发明人： Jung Hwan Lee , Jung Mi Ko , Ji Hwan Kim , Kwang Ho Baek , Young Don Jung
IPC分类号： G11C16/24 , G11C16/34 , G11C16/30 , G11C16/10 , G11C16/08 , G11C11/56 , G11C16/04
摘要： Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.

8. 发明授权

US11107541B2 Memory device and method of operating the memory device 有权
公开(公告)号：US11107541B2
公开(公告)日：2021-08-31
申请号：US15931276
申请日：2020-05-13
申请人： SK hynix Inc.
发明人： Young Don Jung , Jung Mi Ko , Kwang Ho Baek , Chang Han Son , Jung Hwan Lee
IPC分类号： G11C16/34 , G11C16/04 , G11C16/10 , G11C16/24 , G11C11/56 , G11C16/26
摘要： The present technology relates to a memory device and method of operating the memory device. The memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit performs a plurality of program loops each including a program operation and a verify operation on selected memory cells of the plurality of memory cells. The control logic controls the peripheral circuit to increase a potential of selected bit lines.

9. 发明授权

US10998053B2 Memory device and operating method thereof for applying a channel precharge voltage to bit lines after a sensing operation 有权
公开(公告)号：US10998053B2
公开(公告)日：2021-05-04
申请号：US16676157
申请日：2019-11-06
申请人： SK hynix Inc.
发明人： Jung Hwan Lee , Jung Mi Ko , Ji Hwan Kim , Kwang Ho Baek , Young Don Jung
IPC分类号： G11C7/12 , G11C16/24 , G11C16/04 , G11C16/34 , G11C16/26 , G11C16/30 , G11C16/08 , G11C16/16 , G11C8/08
摘要： A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.

10. 发明授权

US10818360B2 Memory device, memory system including the memory device 有权
公开(公告)号：US10818360B2
公开(公告)日：2020-10-27
申请号：US16445932
申请日：2019-06-19
申请人： SK hynix Inc.
发明人： Jong Hoon Lee , Ji Hwan Kim , Kwang Ho Baek , Jin Haeng Lee
IPC分类号： G11C16/10 , G11C16/30 , G11C16/34 , G06F3/06 , G11C16/24 , G11C16/04
摘要： The present disclosure relates to a memory device and a memory system including the same. The memory device includes a memory cell storing data, a voltage generation circuit selectively outputting a program voltage and verify voltages in response to an operation control signal, a page buffer including first latches and second latches, and storing first data sensed by a first sensing current in the first latches and second data sensed by a sensing current greater than the first sensing current in the second latches during a verify operation using the verify voltages, and a pass/fail check circuit determining a pass or fail of the verify operation of the memory cell according to the first data and allowable bits.

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