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1. 发明授权

US11037629B2 Semiconductor memory device and method for operating thereof 有权
公开(公告)号：US11037629B2
公开(公告)日：2021-06-15
申请号：US16728363
申请日：2019-12-27
申请人： SK hynix Inc.
发明人： Jung Mi Ko , Kwang Ho Baek , Seong Je Park , Young Don Jung , Ji Hwan Kim , Jung Hwan Lee
IPC分类号： G11C16/08 , G11C16/10 , G11C16/26 , G11C16/34 , G11C16/04
摘要： Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.

2. 发明授权

US08743621B2 Operating method in a non-volatile memory device 有权
标题翻译：非易失性存储器件中的操作方法
公开(公告)号：US08743621B2
公开(公告)日：2014-06-03
申请号：US13759897
申请日：2013-02-05
申请人： SK hynix Inc.
发明人： Seong Je Park
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/3404 , G11C16/3445
摘要： A method of verifying a non-volatile memory device includes precharging a bit line to a high level through a sensing node by applying a first voltage to a bit line select transistor coupled between the bit line and the sensing node; applying a verifying voltage to a plurality of word lines; disconnecting the bit line from the sensing node; and coupling the bit line to the sensing node by applying a second voltage to the bit line select transistor so as to detect a level of the bit line, the second voltage being smaller than the first voltage, wherein, a difference between the first voltage and the second voltage in a verifying operation is higher than a difference between a first voltage and a second voltage that are used in a read operation.
摘要翻译：一种验证非易失性存储器件的方法包括：通过将耦合在位线和检测节点之间的位线选择晶体管施加第一电压，通过感测节点将位线预充电到高电平; 向多个字线施加验证电压; 断开位线与感测节点的连接; 以及通过向所述位线选择晶体管施加第二电压来将所述位线耦合到所述感测节点，以便检测所述位线的电平，所述第二电压小于所述第一电压，其中，所述第一电压和验证操作中的第二电压高于在读取操作中使用的第一电压和第二电压之间的差。

3. 发明授权

US08767481B2 Nonvolatile memory device and method of operating the same 有权
标题翻译：非易失存储器件及其操作方法
公开(公告)号：US08767481B2
公开(公告)日：2014-07-01
申请号：US13648566
申请日：2012-10-10
申请人： SK hynix Inc.
发明人： Myung Cho , Seong Je Park , Jung Hwan Lee , Ji Hwan Kim , Beom Seok Hah
IPC分类号： G11C7/10
CPC分类号： G11C7/1048 , G11C7/10 , G11C16/3459 , G11C2216/14
摘要： A nonvolatile memory device includes a page buffer unit configured to include a plurality of page buffers coupled to the respective bit lines; a pass/fail circuit coupled to the page buffer unit and configured to perform a pass/fail check operation by comparing the amount of current, varying according to verify data stored in the plurality of page buffers, with an amount of reference current corresponding to the number of allowed error correction code bits; and a masking circuit configured to preclude the pass/fail check operation by coupling a ground terminal to sense nodes coupled to the remaining page buffers, respectively, other than page buffers corresponding to column addresses having the identical upper bits as an input column address.
摘要翻译：非易失性存储器件包括：页缓冲器单元，被配置为包括耦合到相应位线的多个页缓冲器; 耦合到页面缓冲单元的通过/失败电路，并且被配置为通过比较根据存储在多个页面缓冲器中的验证数据而变化的电流量与对应于多个页面缓冲器的参考电流量进行比较来执行通过/失败检查操作允许纠错码位数; 以及屏蔽电路，被配置为通过将接地端子分别耦合到感测与剩余页缓冲器相耦合的节点来排除通过/失败检查操作，除了对应于具有相同高位的列地址的页缓冲器作为输入列地址之外。

4. 发明授权

US11636898B2 Semiconductor memory device and method for operating thereof 有权
公开(公告)号：US11636898B2
公开(公告)日：2023-04-25
申请号：US17337936
申请日：2021-06-03
申请人： SK hynix Inc.
发明人： Jung Mi Ko , Kwang Ho Baek , Seong Je Park , Young Don Jung , Ji Hwan Kim , Jung Hwan Lee
IPC分类号： G11C16/16 , G11C16/10 , G11C16/26 , G11C16/34 , G11C16/08 , G11C16/04
摘要： Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.

5. 发明授权

US10937513B2 Semiconductor memory device and operating method thereof 有权
公开(公告)号：US10937513B2
公开(公告)日：2021-03-02
申请号：US16667760
申请日：2019-10-29
申请人： SK hynix Inc.
发明人： Jung Mi Ko , Kwang Ho Baek , Ji Hwan Kim , Seong Je Park , Sung Hoon Ahn , Young Don Jung
IPC分类号： G11C16/34 , H01L27/11556 , H01L27/11582 , G11C16/10 , G11C16/04 , G11C11/56
摘要： A semiconductor memory device operates by applying a program pulse to a selected word line, updating a program pulse count value, determining a current sensing mode based upon the program pulse count value, and performing a program verify operation based upon the current sensing mode. The current sensing mode is determined by determining one of an individual state current sensing operation for determining verify pass or fail for one target program state and an all-state current sensing operation for determining verify pass or fail for all target program states.

6. 发明授权

US09293211B2 Semiconductor device and method of operating the same 有权
标题翻译：半导体装置及其操作方法
公开(公告)号：US09293211B2
公开(公告)日：2016-03-22
申请号：US14106559
申请日：2013-12-13
申请人： SK hynix Inc.
发明人： Seong Je Park
IPC分类号： G11C11/34 , G11C16/26 , G11C16/34 , G11C11/56 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3459
摘要： A semiconductor memory device includes a memory cell, a page buffer including a first and a second switching devices coupled in common to a sensing node coupled to the memory cell through a bit line and a first and a second sensing latch units coupled to the sensing node, respectively, through the first and the second switching devices, and a control logic suitable for transferring a first and a second sensing signals, respectively, to the first and the second switching devices when a threshold voltage of the memory cell is reflected on the sensing node through the bit line during a verification operation. The first and the second switching devices are turned on or off, respectively, in response to the first and the second sensing signals, and data are sensed by the first and the second sensing latch units.
摘要翻译：半导体存储器件包括存储单元，页缓冲器，其包括第一和第二开关器件，其共同耦合到通过位线耦合到存储器单元的感测节点以及耦合到感测节点的第一和第二感测锁存单元分别通过第一和第二开关装置，以及控制逻辑，适于在第一和第二开关装置的阈值电压反映在第一和第二开关装置的感测上时分别传送第一和第二感测信号节点在验证操作期间通过位线。第一和第二开关装置分别响应于第一和第二感测信号而导通或关断，并且数据由第一和第二感测锁存单元感测。

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