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1. 发明申请

US20160372205A1 SENSE AMPLIFIER DESIGN FOR RAMP SENSING 有权
标题翻译：感测放大器设计用于RAMP感应
公开(公告)号：US20160372205A1
公开(公告)日：2016-12-22
申请号：US14924118
申请日：2015-10-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： Anirudh Amarnath , Tai-Yuan Tseng
IPC分类号： G11C16/26 , G11C16/30
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/32
摘要： Methods and systems for sensing memory cells using a sense amplifier that can support both ramp sensing and conventional sensing are described. With ramp sensing, a word line of a memory array may be ramped up linearly and a sensing operation may be performed by the sense amplifier while the word line is continuously being ramped up. In this case, during the sensing operation, the sense amplifier may sense a bit line of the memory array connected to a memory cell while the word line is ramping up and then transfer the result into a data latch. In contrast, with conventional sensing, a bit line of the memory array may be first precharged to a particular voltage level (e.g., a read voltage level) and then sensed while the word line is held at the particular voltage level.
摘要翻译：描述了使用可支持斜坡感测和常规感测的读出放大器来感测存储单元的方法和系统。通过斜坡感测，存储器阵列的字线可以线性地斜坡上升，并且当字线连续地上升时，感测放大器可以执行感测操作。在这种情况下，在感测操作期间，读出放大器可以感测连接到存储器单元的存储器阵列的位线，同时字线正在上升，然后将结果传送到数据锁存器。相比之下，对于常规感测，存储器阵列的位线可以首先被预充电到特定电压电平（例如，读取电压电平），然后在字线保持在特定电压电平的同时被感测。

2. 发明授权

US09437302B2 State-dependent lockout in non-volatile memory 有权
标题翻译：非易失性存储器中的状态依赖锁定
公开(公告)号：US09437302B2
公开(公告)日：2016-09-06
申请号：US14616309
申请日：2015-02-06
申请人： SanDisk Technologies Inc.
发明人： Tai-Yuan Tseng , Cynthia Hsu , Kwang Ho Kim
IPC分类号： G11C11/34 , G11C16/10 , G11C16/34 , G11C11/56 , G11C16/26 , G11C16/24
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3459
摘要： A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier scans program data prior to sensing at the verify levels corresponding to a plurality of states. When program data matches a currently selected state, the sense amplifier senses the bit line voltage during verification and writes the result to a data latch. The sense amplifier may write the result to a data latch for storing quick pass write data, in response to sensing at a low verify level for the selected state for example. When program data does not match the currently selected state, the sense amplifier skips sensing for the bit line. The sense amplifier locks out the bit line prior to sensing based on the program data.
摘要翻译：读出放大器提供状态相关的锁定，以将感测限制到目标为当前选择的状态用于感测的那些位线。感测放大器在对应于多个状态的验证电平进行感测之前扫描程序数据。当程序数据与当前选择的状态相匹配时，读出放大器在验证期间感测位线电压，并将结果写入数据锁存器。响应于针对例如选定状态的低验证电平的感测，读出放大器可将结果写入用于存储快速写入数据的数据锁存器。当程序数据与当前选择的状态不匹配时，读出放大器跳过位线的检测。读出放大器根据程序数据在感测之前锁定位线。

3. 发明申请

US20150221348A1 Sense Amplifier With Efficient Use Of Data Latches 有权
标题翻译：有效利用数据锁存器的检测放大器
公开(公告)号：US20150221348A1
公开(公告)日：2015-08-06
申请号：US14616289
申请日：2015-02-06
申请人： SanDisk Technologies Inc.
发明人： Tai-Yuan Tseng , Yenlung Li , Cynthia Hsu , Kwang Ho Kim , Man L. Mui
IPC分类号： G11C7/06 , G06F3/06 , G11C16/26
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3459
摘要： A non-volatile memory includes an efficient data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.
摘要翻译：非易失性存储器包括用于使用至少三个编程级别对位线进行编程的有效数据锁存结构。读出放大器包括用于控制相应位线的电压的第一数据锁存器和具有扫描电路的第二静态数据锁存器，用于对程序数据执行逻辑运算并感测结果。读出放大器利用程序数据扫描低校验感应结果，以产生简化的编程数据。在感测所有状态之后，将减少的编程数据从第一数据锁存器传送出去，并且扫描程序数据以产生存储在第一数据锁存器中的程序使能/禁止数据。在将位线设置为程序禁止或程序使能电平之后，减小的编程数据被传送回第一数据锁存器。然后，用于减少编程的位线被调整到降低的编程电平。

4. 发明授权

US09892791B2 Fast scan to detect bit line discharge time 有权
公开(公告)号：US09892791B2
公开(公告)日：2018-02-13
申请号：US15184939
申请日：2016-06-16
申请人： SANDISK TECHNOLOGIES INC.
发明人： Yen-Lung Li , Jong Yuh , Jonathan Huynh , Tai-Yuan Tseng , Kwang-Ho Kim , Qui Nguyen
IPC分类号： G11C16/08 , G11C16/26 , G11C16/34 , G11C7/04 , G11C16/04
CPC分类号： G11C16/08 , G11C7/04 , G11C16/0483 , G11C16/26 , G11C16/3459
摘要： Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.

5. 发明授权

US09711211B2 Dynamic threshold voltage compaction for non-volatile memory 有权
公开(公告)号：US09711211B2
公开(公告)日：2017-07-18
申请号：US14926180
申请日：2015-10-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Muhammad Masuduzzaman , Tai-Yuan Tseng , Huai-Yuan Tseng , Deepanshu Dutta
IPC分类号： G11C16/00 , G11C11/56 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3468
摘要： Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.

6. 发明申请

US20170117024A1 BIT LINE CHARGING FOR A DEVICE 有权
公开(公告)号：US20170117024A1
公开(公告)日：2017-04-27
申请号：US14924498
申请日：2015-10-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： Anirudh Amarnath , Tai-Yuan Tseng
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/02 , G11C11/5628 , G11C16/10 , G11C16/12 , G11C16/24
摘要： An apparatus includes a first bit line coupled to a first storage element and a second bit line coupled to a second storage element. A first bit line charging circuit is coupled to the first bit line and is configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state. A second bit line charging circuit is coupled to the second bit line and is configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state. The second programming state is different than the first programming state.

7. 发明授权

US09552882B2 Sense amplifier with efficient use of data latches 有权
标题翻译：感应放大器，有效利用数据锁存器
公开(公告)号：US09552882B2
公开(公告)日：2017-01-24
申请号：US14616289
申请日：2015-02-06
申请人： SanDisk Technologies Inc.
发明人： Tai-Yuan Tseng , Yenlung Li , Cynthia Hsu , Kwang Ho Kim , Man L Mui
IPC分类号： G06F12/00 , G11C16/10 , G11C16/34 , G11C11/56 , G11C16/26 , G11C16/24
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3459
摘要： A non-volatile memory includes an data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.
摘要翻译：非易失性存储器包括用于使用至少三个编程电平对位线进行编程的数据锁存结构。读出放大器包括用于控制相应位线的电压的第一数据锁存器和具有扫描电路的第二静态数据锁存器，用于对程序数据执行逻辑运算并感测结果。读出放大器利用程序数据扫描低校验感应结果，以产生简化的编程数据。在对所有状态进行感测之后，减少的编程数据被传送出第一数据锁存器，并且扫描程序数据以产生存储在第一数据锁存器中的程序使能/禁止数据。在将位线设置为程序禁止或程序使能电平之后，减小的编程数据被传送回第一数据锁存器。然后，用于减少编程的位线被调整到降低的编程电平。

8. 发明申请

US20160351254A1 MULTI-STATE PROGRAMMING FOR NON-VOLATILE MEMORY 有权
标题翻译：用于非易失性存储器的多状态编程
公开(公告)号：US20160351254A1
公开(公告)日：2016-12-01
申请号：US14929156
申请日：2015-10-30
申请人： SanDisk Technologies Inc.
发明人： Yen-Lung Li , Raul-Adrian Cernea , Jong Hak Yuh , Tai-Yuan Tseng
IPC分类号： G11C11/56 , G11C16/24
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/107 , G11C16/24 , G11C2211/5622
摘要： A method is provided for programming a non-volatile memory. The method includes programming memory cells for even bit lines by programming the memory cells into a plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to a plurality of target data states. The method also includes programming memory cells for odd bit lines by programming the memory cells into the plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to the plurality of target data states.
摘要翻译：提供了一种用于对非易失性存储器进行编程的方法。该方法包括通过将存储器单元编程为从擦除状态的多个中间数据状态以及对于每个中间数据状态，同时将存储器单元编程为多个目标数据状态来编程用于偶数位线的存储器单元。该方法还包括通过将存储器单元从擦除状态编程成多个中间数据状态，并且对于每个中间数据状态，同时将存储器单元编程为多个目标数据状态，来编程用于奇数位线的存储器单元。

9. 发明申请

US20150221391A1 State-Dependent Lockout In Non-Volatile Memory 有权
标题翻译：非易失性存储器中的状态锁定
公开(公告)号：US20150221391A1
公开(公告)日：2015-08-06
申请号：US14616309
申请日：2015-02-06
申请人： SanDisk Technologies Inc.
发明人： Tai-Yuan Tseng , Cynthia Hsu , Kwang Ho Kim
IPC分类号： G11C16/34 , G11C16/26 , G11C16/24 , G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3459
摘要： A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier scans program data prior to sensing at the verify levels corresponding to a plurality of states. When program data matches a currently selected state, the sense amplifier senses the bit line voltage during verification and writes the result to a data latch. The sense amplifier may write the result to a data latch for storing quick pass write data, in response to sensing at a low verify level for the selected state for example. When program data does not match the currently selected state, the sense amplifier skips sensing for the bit line. The sense amplifier locks out the bit line prior to sensing based on the program data.
摘要翻译：读出放大器提供状态相关的锁定，以将感测限制到目标为当前选择的状态用于感测的那些位线。感测放大器在对应于多个状态的验证电平进行感测之前扫描程序数据。当程序数据与当前选择的状态相匹配时，读出放大器在验证期间感测位线电压，并将结果写入数据锁存器。响应于针对例如选定状态的低验证电平的感测，读出放大器可将结果写入用于存储快速写入数据的数据锁存器。当程序数据与当前选择的状态不匹配时，读出放大器跳过位线的检测。读出放大器根据程序数据在感测之前锁定位线。

10. 发明授权

US10014063B2 Smart skip verify mode for programming a memory device 有权
公开(公告)号：US10014063B2
公开(公告)日：2018-07-03
申请号：US14928853
申请日：2015-10-30
申请人： SanDisk Technologies Inc.
发明人： Huai-Yuan Tseng , Deepanshu Dutta , Tai-Yuan Tseng , Grishma Shah , Muhammad Masuduzzaman
IPC分类号： G11C16/34 , G11C16/10 , G11C11/56
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/0409 , G11C2029/1202
摘要： Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.

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