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1. 发明授权

US09633233B2 Method and computing device for encrypting data stored in swap memory 有权
公开(公告)号：US09633233B2
公开(公告)日：2017-04-25
申请号：US14272255
申请日：2014-05-07
申请人： SanDisk Technologies Inc.
发明人： Robert S. Wu , Jian Chen , Ashish Karkare , Alon Marcu , Vsevolod Mountaniol
IPC分类号： G06F11/30 , G06F21/79 , G06F12/02 , G06F12/0862
CPC分类号： G06F21/79 , G06F12/023 , G06F12/0862 , G06F2212/7201
摘要： The following embodiments generally relate to the use of a “swap area” in a non-volatile memory as an extension to volatile memory in a computing device. These embodiments include techniques to use both volatile memory and non-volatile swap memory to pre-load a plurality of applications, to control the bandwidth of swap operations, to encrypt data stored in the swap area, and to perform a fast clean-up of the swap area.

2. 发明授权

US09595342B2 Method and apparatus for refresh programming of memory cells based on amount of threshold voltage downshift 有权
标题翻译：基于阈值电压降档量的存储器单元刷新编程的方法和装置
公开(公告)号：US09595342B2
公开(公告)日：2017-03-14
申请号：US14600365
申请日：2015-01-20
申请人： SanDisk Technologies Inc.
发明人： Liang Pang , Yingda Dong , Jian Chen
IPC分类号： G11C16/34 , G11C16/26 , G11C16/10 , G11C11/56
CPC分类号： G11C16/3431 , G11C11/5621 , G11C11/5671 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3459
摘要： Techniques are provided for periodically monitoring and adjusting the threshold voltage levels of memory cells in a charge-trapping memory device. When a criterion is met, such as based on the passage of a specified time period, the memory cells are read to classify them into different subsets according to an amount of downshift in threshold voltage (Vth). Two or more subsets can be used per data state. A subset can also comprise cells which are corrected using Error Correction Code (ECC) decoding. The subsets of memory cells are refresh programmed, without being erased, in which a Vth upshift is provided in proportion to the Vth downshift. The refresh programming can use a fixed or adaptive number of program pulses per subset. Some cells will have no detectable Vth downshift or a minor amount of Vth downshift which can be ignored. These cells need not be refresh programmed.
摘要翻译：提供了用于周期性地监测和调整电荷俘获存储器件中的存储器单元的阈值电压电平的技术。当满足标准时，例如基于指定时间段的过去，存储器单元被读取以根据阈值电压（Vth）的降档量将它们分类成不同的子集。每个数据状态可以使用两个或多个子集。子集还可以包括使用纠错码（ECC）解码来校正的单元。存储器单元的子集被刷新编程，而不被擦除，其中与Vth降档成比例地提供Vth升档。刷新编程可以使用每个子集的固定或自适应编程脉冲数。一些电池将没有可检测的Vth降档或少量的Vth降档，这可以被忽略。这些单元不需要刷新编程。

3. 发明申请

US20160211023A1 OPERATION MODES FOR AN INVERTED NAND ARCHITECTURE 有权
标题翻译：反向NAND架构的操作模式
公开(公告)号：US20160211023A1
公开(公告)日：2016-07-21
申请号：US15083224
申请日：2016-03-28
申请人： SANDISK TECHNOLOGIES INC.
发明人： Yanli Zhang , George Samachisa , Johann Alsmeier , Jian Chen
IPC分类号： G11C16/04 , G11C16/10 , G11C16/26
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/10 , G11C16/26
摘要： Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.
摘要翻译：描述了对包括反相NAND串的存储器阵列执行存储器操作的方法。存储器操作可以包括擦除操作，读取操作，编程操作，程序验证操作和擦除验证操作。反相NAND串可以包括一串反向浮栅晶体管或一串反向电荷陷阱晶体管。在一个实施例中，反向浮栅晶体管可以包括在反相浮栅晶体管的浮置栅极和反相浮栅晶体管的控制栅极之间的隧穿层。浮动栅极和控制栅极之间的隧道层的布置允许电子通过浮动栅极和控制栅极之间的F-N隧穿而被添加到浮动栅极或从浮动栅极去除。反相NAND串可以形成在衬底之上并且被定向成使得反相NAND串与衬底正交。

4. 发明申请

US20160118131A1 Adaptive Program Pulse Duration Based On Temperature 有权
标题翻译：基于温度的自适应编程脉冲持续时间
公开(公告)号：US20160118131A1
公开(公告)日：2016-04-28
申请号：US14522901
申请日：2014-10-24
申请人： SanDisk Technologies Inc.
发明人： Yingda Dong , Jiahui Yuan , Jian Chen
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/3427 , G11C7/04 , G11C16/10 , G11C16/3431 , G11C16/3459
摘要： Techniques are provided for reducing program disturb in a memory device. The techniques include compensating for a temperature in the memory device to reduce the upshift in the threshold voltage (Vth) of erased-state memory cells. A minimum allowable program pulse duration increases with temperature to account for an increase in the attenuation of a program pulse along a word line. A program pulse duration which accounts for reduced channel boosting at relatively high temperatures is reduced as the temperature increases. An optimum program pulse duration is based on the larger of these durations. The optimum program pulse duration can also be based on factors such as a measure of program disturb or a memory hole width. Program disturb can also be reduced by easing the requirements of a verify test for the highest data state.
摘要翻译：提供了用于减少存储器件中的程序干扰的技术。这些技术包括补偿存储器件中的温度以减少擦除状态存储器单元的阈值电压（Vth）的升档。最小可允许编程脉冲持续时间随着温度而增加，以增加沿着字线的编程脉冲的衰减。在相对较高的温度下减少通道增压的程序脉冲持续时间随着温度的升高而降低。最佳编程脉冲持续时间是基于这些持续时间中较大的一个。最佳编程脉冲持续时间也可以基于诸如程序干扰的测量或存储器孔宽度的因素。程序干扰也可以通过缓解对最高数据状态的验证测试的要求来降低。

5. 发明授权

US09245642B1 Temperature dependent voltage to unselected drain side select transistor during program of 3D NAND 有权
标题翻译：在3D NAND程序期间与未选择的漏极侧选择晶体管的温度相关电压
公开(公告)号：US09245642B1
公开(公告)日：2016-01-26
申请号：US14673265
申请日：2015-03-30
申请人： SanDisk Technologies Inc.
发明人： Jian Chen , Yingda Dong , Jiahui Yuan
IPC分类号： G11C16/04 , G11C16/34 , G11C16/10 , G11C11/56
CPC分类号： G11C16/3427 , G11C7/04 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3418 , G11C16/349
摘要： Techniques are provided for reducing program disturb in a 3D memory device. The techniques include compensating for a temperature dependence of program disturb. The techniques may include compensating for how program disturb depends on the location of the word line that is selected for programming. In one aspect, the voltage that is applied to the control gates drain side select transistors of unselected NAND strings is adjusted during programming based on temperature. Greater temperature compensation may be applied when the selected word line is closer to the drain side select transistors.
摘要翻译：提供了用于减少3D存储器件中的程序干扰的技术。这些技术包括补偿程序干扰的温度依赖性。这些技术可以包括补偿程序干扰如何依赖于被选择用于编程的字线的位置。在一个方面，在基于温度的编程期间调整施加到未选择的NAND串的控制栅极漏极侧选择晶体管的电压。当所选择的字线更靠近漏极侧选择晶体管时，可以施加更大的温度补偿。

6. 发明授权

US09218890B2 Adaptive operation of three dimensional memory 有权
公开(公告)号：US09218890B2
公开(公告)日：2015-12-22
申请号：US13908921
申请日：2013-06-03
申请人： SanDisk Technologies Inc.
发明人： Chris Nga Yee Avila , Gautam Ashok Dusija , Jian Chen , Yingda Dong , Man Lung Mui , Seungpil Lee , Alexander Kwok-Tung Mak
IPC分类号： G11C11/34 , G11C16/34 , G11C29/04 , G06F11/10 , G06F11/14
CPC分类号： G11C16/3404 , G06F11/1048 , G06F11/141 , G06F11/1497 , G11C29/04
摘要： When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit.

7. 发明授权

US09009398B2 Write operations for defect management in nonvolatile memory 有权
公开(公告)号：US09009398B2
公开(公告)日：2015-04-14
申请号：US14281432
申请日：2014-05-19
申请人： SanDisk Technologies Inc.
发明人： Chris Avila , Gautam Dusija , Jian Chen , Mrinal Kochar , Abhijeet Manohar
IPC分类号： G06F12/00 , G06F11/10 , G11C29/52
CPC分类号： G06F11/1072 , G06F12/0246 , G06F2212/7209 , G11C11/5628 , G11C16/3418 , G11C29/52 , G11C2029/0411 , G11C2211/5641
摘要： Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory.

8. 发明申请

US20150006784A1 Efficient Post Write Read in Three Dimensional Nonvolatile Memory 审中-公开
标题翻译：在三维非易失性存储器中高效写入读取
公开(公告)号：US20150006784A1
公开(公告)日：2015-01-01
申请号：US13929368
申请日：2013-06-27
申请人： SanDisk Technologies Inc.
发明人： Chris Nga Yee Avila , Gautam Ashok Dusija , Jian Chen
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C2211/5621 , G11C2211/5641
摘要： Data that is stored in a higher error rate format in a 3-D nonvolatile memory is backed up in a lower error rate format. Later, the higher error rate copy is sampled to determine if it is acceptable. A sampling pattern samples all word lines of a string and at least one word line of each string of the block.
摘要翻译：在3-D非易失性存储器中以较高错误率格式存储的数据以较低的错误率格式进行备份。之后，对较高的错误率副本进行采样，以确定是否可以接受。采样模式对字符串的所有字线和块的每个字符串的至少一个字线进行采样。

9. 发明申请

US20150003161A1 System for Maintaining Back Gate Threshold Voltage in Three Dimensional NAND Memory 有权
标题翻译：用于维持三维NAND存储器中的后门限电压的系统
公开(公告)号：US20150003161A1
公开(公告)日：2015-01-01
申请号：US13927659
申请日：2013-06-26
申请人： SanDisk Technologies Inc.
发明人： Chris Nga Yee Avila , Gautam Ashok Dusija , Yingda Dong , Jian Chen , Man Lung Mui , Alexander Kwok-Tung Mak , Seungpil Lee
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3427 , G11C29/021 , G11C29/028
摘要： In a nonvolatile memory array in which a NAND string includes a back gate that has a charge storage element, the threshold voltage of the back gate is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range.
摘要翻译：在其中NAND串包括具有电荷存储元件的背栅的非易失性存储器阵列中，监视背栅的阈值电压，并且如果阈值电压偏离期望的阈值电压范围，则将电荷加到或从电荷存储元件移除以将阈值电压返回到期望的阈值电压范围。

10. 发明授权

US08918577B1 Three dimensional nonvolatile memory with variable block capacity 有权
标题翻译：具有可变块容量的三维非易失性存储器
公开(公告)号：US08918577B1
公开(公告)日：2014-12-23
申请号：US14304562
申请日：2014-06-13
申请人： SanDisk Technologies Inc.
发明人： Sergey Anatolievich Gorobets , Jian Chen
IPC分类号： G06F12/00 , G06F3/06
CPC分类号： G11C11/5621 , G11C5/02 , G11C8/12 , G11C16/0483 , G11C2211/5641 , G11C2213/71
摘要： In a three-dimensional nonvolatile memory, physical levels in blocks are zoned and different zones store different numbers of bits per cell so that different blocks have different data capacities. Block data capacities are calculated and recorded, and may be updated as data capacities change. User data is mapped to blocks according to their respective data capacities.
摘要翻译：在三维非易失性存储器中，块中的物理电平被划分并且不同的区域存储每个单元的不同数量的位，使得不同的块具有不同的数据容量。块数据容量被计算和记录，并且可以随数据容量的变化而更新。用户数据根据各自的数据容量映射到块。

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