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1. 发明授权

US09911500B2 Dummy voltage to reduce first read effect in memory 有权
公开(公告)号：US09911500B2
公开(公告)日：2018-03-06
申请号：US15131392
申请日：2016-04-18
申请人： SanDisk Technologies Inc.
发明人： Liang Pang , Pao-ling Koh , Jiahui Yuan , Charles Kwong , Yingda Dong
IPC分类号： G11C16/06 , G11C16/28 , G11C16/10 , G11C16/26 , G11C16/04 , G11C16/34
CPC分类号： G11C16/28 , G11C7/14 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C2211/5621
摘要： Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. In one aspect, a dummy voltage is applied to the word lines to cause a coupling up of the word lines and weak programming. This can occur when a specified amount of time has elapsed since a last program or read operation, or when a power on event is detected for the memory device. A number of read errors can also be considered. The dummy voltage is similar to a pass voltage of a program or read operation but no sensing is performed. The word line voltages are therefore provided at a consistently up-coupled level so that read operations are consistent. The coupling up occurs due to capacitive coupling between the word line and the channel.

2. 发明申请

US20170301403A1 Dummy Voltage To Reduce First Read Effect In Memory 有权
公开(公告)号：US20170301403A1
公开(公告)日：2017-10-19
申请号：US15131392
申请日：2016-04-18
申请人： SanDisk Technologies Inc.
发明人： Liang Pang , Pao-ling Koh , Jiahui Yuan , Charles Kwong , Yingda Dong
IPC分类号： G11C16/28 , G11C16/26 , G11C16/10 , G11C16/34 , G11C16/04
CPC分类号： G11C16/28 , G11C7/14 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C2211/5621
摘要： Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. In one aspect, a dummy voltage is applied to the word lines to cause a coupling up of the word lines and weak programming. This can occur when a specified amount of time has elapsed since a last program or read operation, or when a power on event is detected for the memory device. A number of read errors can also be considered. The dummy voltage is similar to a pass voltage of a program or read operation but no sensing is performed. The word line voltages are therefore provided at a consistently up-coupled level so that read operations are consistent. The coupling up occurs due to capacitive coupling between the word line and the channel.

3. 发明授权

US09437318B2 Adaptive program pulse duration based on temperature 有权
标题翻译：基于温度的自适应编程脉冲持续时间
公开(公告)号：US09437318B2
公开(公告)日：2016-09-06
申请号：US14522901
申请日：2014-10-24
申请人： SanDisk Technologies Inc.
发明人： Yingda Dong , Jiahui Yuan , Jian Chen
IPC分类号： G11C11/34 , G11C16/34 , G11C16/10
CPC分类号： G11C16/3427 , G11C7/04 , G11C16/10 , G11C16/3431 , G11C16/3459
摘要： Techniques are provided for reducing program disturb in a memory device. The techniques include compensating for a temperature in the memory device to reduce the upshift in the threshold voltage (Vth) of erased-state memory cells. A minimum allowable program pulse duration increases with temperature to account for an increase in the attenuation of a program pulse along a word line. A program pulse duration which accounts for reduced channel boosting at relatively high temperatures is reduced as the temperature increases. An optimum program pulse duration is based on the larger of these durations. The optimum program pulse duration can also be based on factors such as a measure of program disturb or a memory hole width. Program disturb can also be reduced by easing the requirements of a verify test for the highest data state.
摘要翻译：提供了用于减少存储器件中的程序干扰的技术。这些技术包括补偿存储器件中的温度以减少擦除状态存储器单元的阈值电压（Vth）的升档。最小可允许编程脉冲持续时间随着温度而增加，以增加沿着字线的编程脉冲的衰减。在相对较高的温度下减少通道增压的程序脉冲持续时间随着温度的升高而降低。最佳编程脉冲持续时间是基于这些持续时间中较大的一个。最佳编程脉冲持续时间也可以基于诸如程序干扰的测量或存储器孔宽度的因素。程序干扰也可以通过缓解对最高数据状态的验证测试的要求来降低。

4. 发明授权

US09406387B2 Charge redistribution during erase in charge trapping memory 有权
标题翻译：在电荷捕获存储器中的擦除期间的电荷再分配
公开(公告)号：US09406387B2
公开(公告)日：2016-08-02
申请号：US14851639
申请日：2015-09-11
申请人： SanDisk Technologies Inc.
发明人： Jiahui Yuan , Ching-Huang Lu , Yingda Dong
IPC分类号： G11C16/04 , G11C16/14 , G11C16/34 , G11C16/16 , G11C11/56 , G11C16/26 , H01L27/115
CPC分类号： G11C16/14 , G11C11/5635 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/344 , G11C16/3445 , G11C2211/5621 , H01L27/11582
摘要： Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole.
摘要翻译：提供了技术来加速与擦除操作相关的孔的再分配，使得在编程之后孔将再次分配。因此，编程后的短期电荷损失减少。在一个方面，在擦除和编程之前，将一个正的控制栅极电压施加到一组存储器单元。与编程电压相比，正控制栅极电压具有相对较低的幅度和长的持续时间。可以基于存储器单元的擦除深度和诸如编程擦除周期的计数，擦除验证迭代的计数，下部尾部的位置的感测以及交叉点的位移等因素来调整正控制栅极电压。存储孔的垂直柱的截面宽度。

5. 发明申请

US20160064090A1 Charge Redistribution During Erase In Charge Trapping Memory 有权
公开(公告)号：US20160064090A1
公开(公告)日：2016-03-03
申请号：US14851639
申请日：2015-09-11
申请人： SanDisk Technologies Inc.
发明人： Jiahui Yuan , Ching-Huang Lu , Yingda Dong
IPC分类号： G11C16/14 , G11C16/26 , G11C16/34 , G11C16/04
CPC分类号： G11C16/14 , G11C11/5635 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/344 , G11C16/3445 , G11C2211/5621 , H01L27/11582
摘要： Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole.

6. 发明授权

US09159406B2 Single-level cell endurance improvement with pre-defined blocks 有权
标题翻译：单级电池耐久性改进与预定义块
公开(公告)号：US09159406B2
公开(公告)日：2015-10-13
申请号：US13668160
申请日：2012-11-02
申请人： SanDisk Technologies Inc.
发明人： Masaaki Higashitani , Mohan Dunga , Jiahui Yuan
IPC分类号： G11C11/34 , G11C16/04 , G11C11/56 , H01L21/28 , H01L27/115
CPC分类号： G11C11/5628 , G11C2211/5641 , H01L21/28273 , H01L27/11521 , H01L27/11524
摘要： Techniques are disclosed for SLC blocks having different characteristics than MLC blocks such that SLC blocks will have high endurance and MLC blocks will have high reliability. A thinner tunnel oxide may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner tunnel oxide in SLC blocks may allow a lower program voltage to be used, which may improve endurance. A thicker tunnel oxide in MLC blocks may improve data retention. A thinner IPD may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner IPD may provide a higher coupling ratio, which may allow a lower program voltage. A lower program voltage in SLC blocks can improve endurance. A thicker IPD in MLC blocks can prevent or reduce read disturb. SLC blocks may have a different number of data word lines than MLC blocks.
摘要翻译：公开了具有与MLC块不同特性的SLC块的技术，使得SLC块将具有高耐久性，并且MLC块将具有高可靠性。对于SLC块中的存储单元，MLC块中的存储单元可以使用较薄的隧道氧化物。 SLC块中较薄的隧道氧化物可能允许使用较低的编程电压，这可以提高耐久性。 MLC块中较厚的隧道氧化物可能会改善数据保留。 SLC块中的存储器单元可以用于MLC块中的存储单元。更薄的IPD可以提供更高的耦合比，这可能允许较低的编程电压。 SLC块中较低的编程电压可以提高耐久性。 MLC块中较厚的IPD可以防止或减少读取干扰。 SLC块可以具有与MLC块不同数量的数据字线。

7. 发明授权

US09753657B2 Dynamic reconditioning of charge trapped based memory 有权
公开(公告)号：US09753657B2
公开(公告)日：2017-09-05
申请号：US14858480
申请日：2015-09-18
申请人： SanDisk Technologies Inc.
发明人： Nian Niles Yang , James Fitzpatrick , Jiahui Yuan
IPC分类号： G06F12/00 , G06F3/06 , G11C16/16 , G11C16/04 , G11C16/34
CPC分类号： G06F3/0619 , G06F3/065 , G06F3/0688 , G11C16/0466 , G11C16/16 , G11C16/3418 , G11C16/3431 , G11C16/349
摘要： A storage device with a charge trapping (CT) based memory may include improved data retention (DR) performance. The CT memory may be 3D memory that uses a charge storage layer for storing charge may have unique data retention behavior. Memory blocks using a charge storage layer may be dynamically detected and reconditioned and re-programmed to improve memory characteristics, such as data retention. The reconditioning may include a dedicated erase cycle for a block that improves the data retention.

8. 发明申请

US20170083249A1 DYNAMIC RECONDITIONING OF CHARGE TRAPPED BASED MEMORY 有权
公开(公告)号：US20170083249A1
公开(公告)日：2017-03-23
申请号：US14858480
申请日：2015-09-18
申请人： SanDisk Technologies Inc.
发明人： Nian Niles Yang , James Fitzpatrick , Jiahui Yuan
IPC分类号： G06F3/06 , G11C16/04 , G11C16/34 , G11C16/16
CPC分类号： G06F3/0619 , G06F3/065 , G06F3/0688 , G11C16/0466 , G11C16/16 , G11C16/3418 , G11C16/3431 , G11C16/349
摘要： A storage device with a charge trapping (CT) based memory may include improved data retention (DR) performance. The CT memory may be 3D memory that uses a charge storage layer for storing charge may have unique data retention behavior. Memory blocks using a charge storage layer may be dynamically detected and reconditioned and re-programmed to improve memory characteristics, such as data retention. The reconditioning may include a dedicated erase cycle for a block that improves the data retention.

9. 发明授权

US09583198B1 Word line-dependent and temperature-dependent pass voltage during programming 有权
标题翻译：编程期间字线依赖和温度依赖的通过电压
公开(公告)号：US09583198B1
公开(公告)日：2017-02-28
申请号：US15136429
申请日：2016-04-22
申请人： SanDisk Technologies Inc.
发明人： Liang Pang , Yingda Dong , Jiahui Yuan , Jingjian Ren
IPC分类号： G11C16/00 , G11C16/10 , G11C16/04 , G11C16/28
CPC分类号： G11C16/10 , G11C7/04 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/3427 , G11C16/3486
摘要： Techniques are provided for avoiding over-programming which can occur on memory cells connected to a data word line at a source-side of a block of word lines. A gradient in the channel potential is created during a program voltage between the data word line and an adjacent dummy word line. This gradient generates electron-hole pairs which can contribute to over programming, where the over programming is worse at higher temperatures. In one aspect, pass voltages of unselected word lines are set to be relatively lower when the temperature is relatively higher, and when the selected word line is among a set of one or more source-side word lines. On the other hand, the pass voltages are set to be relatively higher when the temperature is relatively higher, and when the selected word line is not among the one or more source-side word lines.
摘要翻译：提供了用于避免可能发生在连接到字线块的源侧的数据字线的存储器单元上的过度编程的技术。在数据字线和相邻的虚拟字线之间的编程电压期间产生沟道电位的梯度。该梯度产生电子 - 空穴对，这可以有助于过度编程，其中过高编程在较高温度下更差。在一个方面，当温度相对较高时，未选择的字线的通过电压被设置为相对较低，并且当所选择的字线在一个或多个源极字线的集合中时。另一方面，当温度相对较高时，并且当所选字线不在一个或多个源极字线之间时，通过电压被设置为相对较高。

10. 发明申请

US20160293266A1 Temperature Dependent Voltage To Unselected Drain Side Select Transistor During Program Of 3D NAND 有权
标题翻译：温度依赖电压到3D NAND程序期间的未选择的漏极侧选择晶体管
公开(公告)号：US20160293266A1
公开(公告)日：2016-10-06
申请号：US14964884
申请日：2015-12-10
申请人： SanDisk Technologies Inc.
发明人： Jian Chen , Yingda Dong , Jiahui Yuan
IPC分类号： G11C16/34 , G11C16/04 , G11C16/10
CPC分类号： G11C16/3427 , G11C7/04 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3418 , G11C16/349
摘要： Techniques are provided for reducing program disturb in a 3D memory device. The techniques include compensating for a temperature dependence of program disturb. The techniques may include compensating for how program disturb depends on the location of the word line that is selected for programming. In one aspect, the voltage that is applied to the control gates drain side select transistors of unselected NAND strings is adjusted during programming based on temperature. Greater temperature compensation may be applied when the selected word line is closer to the drain side select transistors.
摘要翻译：提供了用于减少3D存储器件中的程序干扰的技术。这些技术包括补偿程序干扰的温度依赖性。这些技术可以包括补偿程序干扰如何依赖于被选择用于编程的字线的位置。在一个方面，在基于温度的编程期间调整施加到未选择的NAND串的控制栅极漏极侧选择晶体管的电压。当所选择的字线更靠近漏极侧选择晶体管时，可以施加更大的温度补偿。

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