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    • 1. 发明授权
    • Method for manufacturing semiconductor device
    • 制造半导体器件的方法
    • US07541279B2
    • 2009-06-02
    • US11615105
    • 2006-12-22
    • Sang Chul KimJae Won Han
    • Sang Chul KimJae Won Han
    • H01L21/20
    • H01L21/76874C25D3/38C25D3/58C25D5/022C25D7/123H01L21/2885H01L21/76877
    • A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor substrate on which the first metal is deposited into an electrochemical plating (ECP) solution bath in which a second metal is dissolved, dissolving the first metal in the ECP solution bath, plating the first and second metals dissolved in the ECP solution bath at the same time to gap-fill an alloy of the first and second metals in the contact hole, and removing the alloy using the interlayer insulating layer as an end point in a CMP process to form an alloy interconnection.
    • 提供一种制造半导体器件的方法。 该方法包括以下步骤:在半导体衬底上形成层间绝缘层,选择性地图案化层间绝缘层以形成接触孔;在接触孔的内表面上沉积第一金属;浸没第一金属 沉积到其中溶解有第二金属的电化学电镀(ECP)溶液浴中,将第一金属溶解在ECP溶液浴中,同时电镀溶解在ECP溶液浴中的第一和第二金属以间隙填充 接触孔中的第一和第二金属的合金,并且在CMP工艺中使用层间绝缘层作为终点去除合金以形成合金互连。
    • 3. 发明授权
    • Method for manufacturing MOS transistor of semiconductor device
    • 制造半导体器件的MOS晶体管的方法
    • US07704814B2
    • 2010-04-27
    • US11498680
    • 2006-08-02
    • Hyun Soo ShinJae Won Han
    • Hyun Soo ShinJae Won Han
    • H01L21/336
    • H01L21/823493H01L29/6659H01L29/7833
    • Disclosed is a method for manufacturing a semiconductor device including a low-voltage MOS transistor and a high-voltage MOS transistor. The present method includes a low-voltage well implantation process on a semiconductor substrate to form a first well in a first region of the substrate and a second well in a second region of the substrate; forming first and second gate oxide layers and first and second gate electrodes in the first and second regions, respectively; forming a first photoresist pattern to expose the first region; forming a first LDD region in the first region exposed by the first photoresist pattern and the first gate electrode; removing the first photoresist pattern; forming a second photoresist pattern to expose the second region; forming a second LDD region in the second region exposed by the second photoresist pattern and the second gate electrode; performing a compensational implantation on the second region to adjust a well concentration for the high-voltage MOS transistor; and removing the second photoresist pattern.
    • 公开了一种制造包括低电压MOS晶体管和高压MOS晶体管的半导体器件的方法。 本方法包括在半导体衬底上的低电压阱注入工艺,以在衬底的第一区域中形成第一阱,在衬底的第二区域中形成第二阱; 分别在第一和第二区域中形成第一和第二栅极氧化物层和第一和第二栅电极; 形成第一光致抗蚀剂图案以暴露第一区域; 在由第一光致抗蚀剂图案和第一栅电极暴露的第一区域中形成第一LDD区; 去除第一光致抗蚀剂图案; 形成第二光致抗蚀剂图案以暴露所述第二区域; 在由所述第二光致抗蚀剂图案和所述第二栅电极暴露的所述第二区域中形成第二LDD区域; 在所述第二区域上执行补偿注入以调整所述高压MOS晶体管的阱浓度; 并且去除第二光致抗蚀剂图案。
    • 8. 发明申请
    • ALUMINUM METAL LINE OF A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    • 半导体器件的铝金属线及其制造方法
    • US20090189283A1
    • 2009-07-30
    • US12351365
    • 2009-01-09
    • Jae Won Han
    • Jae Won Han
    • H01L23/522H01L21/768
    • H01L21/32051H01L21/76849H01L21/76865H01L21/76885
    • A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer.
    • 一种形成半导体器件的铝线的方法,其中第一A金属薄层,第一铝层和第一B金属薄层依次施加在层间绝缘层上。 进行光刻工艺以形成金属线图案,并对其进行蚀刻。 在金属线图案上施加金属间介电层。 通过化学机械平面化处理去除第一B金属薄层以形成第一级金属线。 依次施加第二铝层和第二金属薄层。 应用光刻胶,进行光刻工艺以形成金属线图案,并进行蚀刻以形成第二级金属线。 在第二级金属线上施加金属间介电层。 在第二金属间介电层上进行化学机械平面化处理。
    • 9. 发明授权
    • Sputter etch methods
    • 溅射蚀刻方法
    • US06903026B2
    • 2005-06-07
    • US10875125
    • 2004-06-23
    • Jae Won Han
    • Jae Won Han
    • H01L21/302H01L21/3213
    • H01L21/32131
    • A sputter etch method in the semiconductor fabrication is disclosed. A sputter etch method for etching a layer on a semiconductor substrate in a chamber by RF plasma, includes loading a substrate for conditioning into the chamber, depositing a metal coating layer on the inside wall of the chamber by sputter etching the substrate for conditioning in the chamber, unloading the substrate for conditioning from the chamber, loading the semiconductor substrate with the layer, and etching the layer on the semiconductor substrate. Accordingly, the sputter etch method can enhance a reliability for a fabrication process of a semiconductor device under the environment of the substantial decrease in impurity falling probability. In other words, the impurity falling probability can be decreased by coating a metal layer on the wall of the sputter etch chamber employing a wafer on which a barrier metal layer is deposited right before a main lot in a sputter etch process.
    • 公开了半导体制造中的溅射蚀刻方法。 用于通过RF等离子体蚀刻腔室中的半导体衬底上的层的溅射蚀刻方法包括将用于调节的衬底加载到腔室中,通过溅射蚀刻衬底以在衬底的内壁中进行调节来在腔室的内壁上沉积金属涂层 从所述室中卸载用于调理的基板,将所述半导体基板与所述层一起加载,以及蚀刻所述半导体基板上的所述层。 因此,溅射蚀刻方法可以在杂质下降概率显着降低的环境下提高半导体器件的制造工艺的可靠性。 换句话说,可以通过在溅射蚀刻室的壁上涂覆金属层,使用其上在溅射蚀刻工艺中在主批次之前沉积阻挡金属层的晶片来降低杂质落下概率。