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1. 发明授权

US07716264B2 Method and apparatus for performing alignment shifting in a floating-point unit 有权
标题翻译：用于在浮点单元中执行对准移位的方法和装置
公开(公告)号：US07716264B2
公开(公告)日：2010-05-11
申请号：US11205987
申请日：2005-08-16
申请人： Sherman M. Dance , Jeffrey R. Summers , Shivakumar Swaminathan
发明人： Sherman M. Dance , Jeffrey R. Summers , Shivakumar Swaminathan
IPC分类号： G06F15/00
CPC分类号： G06F5/01
摘要： An apparatus for performing alignment shifting in a floating-point unit is disclosed. An alignment shifter includes a shift amount calculator, a set of first level shifters and a set of second level shifter. The shift amount calculator generates one shift amount under a double-precision mode and two shift amounts under a single-precision mode. The first level shifters can concurrently receive two double-precision mantissas under the double-precision mode or two single-precision mantissas under the single-precision mode. The first level of shifts performs small shifts concurrently on the two double-precision mantissas according to the single shift amount, or on the two single-precision mantissas according to the two shift amounts. The second level shifters performs large shifts on outputs from the first level shifters to generate one double-precision floating-point result or two single-precision floating-point results.
摘要翻译：公开了一种用于在浮点单元中进行对准移位的装置。对准移位器包括移位量计算器，一组第一电平移位器和一组第二电平移位器。移位量计算器在双精度模式下产生一个移位量，并在单精度模式下产生两个移位量。第一级移位器可以在双精度模式下同时接收两个双精度尾数，或者在单精度模式下同时接收两个单精度尾数。第一级别的换档根据单位移量在两个双精度尾数上同时执行小移动，或者根据两个移位量在两个单精度尾数上同时进行。第二电平移位器对来自第一电平移位器的输出执行大的移位，以产生一个双精度浮点运算或两个单精度浮点运算结果。

2. 发明授权

US08261276B2 Power-efficient thread priority enablement 有权
标题翻译：高效的线程优先级启用
公开(公告)号：US08261276B2
公开(公告)日：2012-09-04
申请号：US12059576
申请日：2008-03-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
IPC分类号： G06F9/46 , G06F9/00 , G06F13/28 , G06F1/32
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
摘要翻译：一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。说明性实施例确定了处理器的目标功率效率模式。一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。

3. 发明授权

US07644233B2 Apparatus and method for supporting simultaneous storage of trace and standard cache lines 有权
标题翻译：用于支持跟踪标准缓存行的同时存储的装置和方法
公开(公告)号：US07644233B2
公开(公告)日：2010-01-05
申请号：US11538445
申请日：2006-10-04
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/0875 , G06F12/0897 , G06F2212/6082
摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。描述了一种用于索引到缓存中并选择所需行的机制。对缓存中包含哪些行进行控制。当在标签比较步骤中匹配时，提供在轨迹线和常规线之间的选择。

4. 发明申请

US20080250207A1 DESIGN STRUCTURE FOR CACHE MAINTENANCE 审中-公开
标题翻译：高速缓存维护的设计结构
公开(公告)号：US20080250207A1
公开(公告)日：2008-10-09
申请号：US12119375
申请日：2008-05-12
申请人： GORDON T. DAVIS , Richard W. Doing , John D. Jabusch , M.V.V. Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： GORDON T. DAVIS , Richard W. Doing , John D. Jabusch , M.V.V. Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F12/00
CPC分类号： G06F9/3844 , G06F9/3808 , G06F12/0875 , G06F12/127 , G06F2212/1021 , G06F2212/1044
摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the cache. This invention avoids inefficiencies in the cache by removing trace lines experiencing early exits from the cache, or trace lines that are short, by maintaining a few bits of information about the accuracy of the control flow in a trace cache line and using that information in addition to the LRU (Least Recently Used) bits that maintain the recency information of a cache line, in order to make a replacement decision.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。对缓存中包含哪些行进行控制。本发明通过在跟踪高速缓存行中维护关于控制流的准确度的几位信息并且使用该信息来避免高速缓存中的低效率，通过删除经历来自缓存的早期退出的跟踪线或短路的跟踪线到保持高速缓存行的新近度信息的LRU（最近使用的）位，以便进行替换判定。

5. 发明申请

US20080235500A1 STRUCTURE FOR INSTRUCTION CACHE TRACE FORMATION 审中-公开
标题翻译：指令高速缓存追踪形成结构
公开(公告)号：US20080235500A1
公开(公告)日：2008-09-25
申请号：US12131442
申请日：2008-06-02
申请人： GORDON T. DAVIS , Richard W. Doing , John D. Jabusch , M. V.V. Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： GORDON T. DAVIS , Richard W. Doing , John D. Jabusch , M. V.V. Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , G06F9/3806 , G06F9/3808 , G06F9/3844
摘要： A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. Instruction branches are predicted taken or not taken using a highly accurate branch history table (BHT). Branches that are predicted not taken are appended to a trace buffer and the next basic block is constructed from the remaining instructions in the fetch buffer. Branches that are predicted taken flush the remaining fetch buffer and the next address is determined using a Branch Target Address Register (BTAC).
摘要翻译：体现在机器可读存储介质中的设计结构，用于至少一个设计，制造和测试用于单个统一的一级指令高速缓存的设计，其中一些行可以包含跟踪和相同同余类中的其他行的设计可以包含提供与常规高速缓存线一致的指令。使用高度精确的分支历史表（BHT）预测采取或不采用指令分支。预测未采用的分支被附加到跟踪缓冲区，并且下一个基本块是从获取缓冲区中的其余指令构建的。预测的分支将刷新剩余的获取缓冲区，并使用分支目标地址寄存器（BTAC）确定下一个地址。

6. 发明授权

US08386712B2 Structure for supporting simultaneous storage of trace and standard cache lines 失效
标题翻译：用于支持跟踪和标准缓存行同时存储的结构
公开(公告)号：US08386712B2
公开(公告)日：2013-02-26
申请号：US12116676
申请日：2008-05-07
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0864 , G06F12/0875 , G06F12/0897 , G06F2212/6082
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
摘要翻译：体现在用于设计，制造和/或测试用于单个统一级别的一个指令高速缓存的机器可读存储介质中的设计结构，其中一些行可以包含跟踪和相同同余类中的其他行的设计可以包含一致的指令块提供常规的高速缓存线。描述了一种用于索引到缓存中并选择所需行的机制。对缓存中包含哪些行进行控制。当在标签比较步骤中匹配时，提供在轨迹线和常规线之间的选择。

7. 发明授权

US07826399B2 Structure for preventing starvation in a slotted ring data communications network 失效
标题翻译：用于在时隙环数据通信网络中防止饥饿的结构
公开(公告)号：US07826399B2
公开(公告)日：2010-11-02
申请号：US12042612
申请日：2008-03-05
申请人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
发明人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
IPC分类号： H04L12/43
CPC分类号： H04L12/4035 , H04L12/66
摘要： A design structure is provided for a slotted ring network, in which a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.
摘要翻译：为时隙环网提供了一种设计结构，其中节点可以用任何未预留的时隙发送不可再生的时隙预留。该预约限制其他节点在时隙中发送新的分组。当插槽返回环到保留节点时，插槽将可用。优选地，响应于预留节点中的饥饿状况做出预约，其可以以各种方式中的任一种来检测。在可选增强中，预留识别预留节点，并且如果新分组将在保留节点处或之前到达其目的地，则环上的另一个节点可以自由地在保留时隙中发送新分组，并且因此不会干扰预订。

8. 发明申请

US20080130667A1 DISTRIBUTED ARBITRATION MECHANISM FOR RING NETWORKS 审中-公开
标题翻译：用于环网的分布式仲裁机制
公开(公告)号：US20080130667A1
公开(公告)日：2008-06-05
申请号：US11564863
申请日：2006-11-30
申请人： Brian M. Bass , Timothy H. Heil , Michael S. Siegel , Jeffrey R. Summers , Tiffany Tamaddoni-Jahromi , Steven P. VanderWiel
发明人： Brian M. Bass , Timothy H. Heil , Michael S. Siegel , Jeffrey R. Summers , Tiffany Tamaddoni-Jahromi , Steven P. VanderWiel
IPC分类号： H04L12/66
CPC分类号： H04L12/66
摘要： A system for employing a scalable distributed arbitration scheme, including: a plurality of stations interconnected via a ring topology for transferring data between the plurality of stations; and a bus coupling the plurality of stations in the ring topology; wherein each of the plurality of stations on the topology ring is permitted to independently make a decision when to load their data on the topology ring by evaluating a set of inputs.
摘要翻译：一种采用可扩展分布仲裁方案的系统，包括：通过环形拓扑互连的多个站，用于在多个站之间传送数据; 以及耦合所述环形拓扑中的所述多个站的总线; 其中允许拓扑环上的多个站中的每一个通过评估一组输入来独立地决定何时将其数据加载到拓扑环上。

9. 发明申请

US20080114964A1 Apparatus and Method for Cache Maintenance 审中-公开
标题翻译：缓存维护的设备和方法
公开(公告)号：US20080114964A1
公开(公告)日：2008-05-15
申请号：US11559512
申请日：2006-11-14
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/305
CPC分类号： G06F12/0893 , G06F9/3808 , G06F9/3844 , G06F12/0862
摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the cache. This invention avoids inefficiencies in the cache by removing trace lines experiencing early exits from the cache, or trace lines that are short, by maintaining a few bits of information about the accuracy of the control flow in a trace cache line and using that information in addition to the LRU (Least Recently Used) bits that maintain the recency information of a cache line, in order to make a replacement decision.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。对缓存中包含哪些行进行控制。本发明通过在跟踪高速缓存行中维护关于控制流的准确度的几位信息并且使用该信息来避免高速缓存中的低效率，通过删除经历来自缓存的早期退出的跟踪线或短路的跟踪线到保持高速缓存行的新近度信息的LRU（最近使用的）位，以便进行替换判定。

10. 发明授权

US08131976B2 Tracking effective addresses in an out-of-order processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US08131976B2
公开(公告)日：2012-03-06
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/26 , G06F9/34
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

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