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1. 发明授权

US07716264B2 Method and apparatus for performing alignment shifting in a floating-point unit 有权
标题翻译：用于在浮点单元中执行对准移位的方法和装置
公开(公告)号：US07716264B2
公开(公告)日：2010-05-11
申请号：US11205987
申请日：2005-08-16
申请人： Sherman M. Dance , Jeffrey R. Summers , Shivakumar Swaminathan
发明人： Sherman M. Dance , Jeffrey R. Summers , Shivakumar Swaminathan
IPC分类号： G06F15/00
CPC分类号： G06F5/01
摘要： An apparatus for performing alignment shifting in a floating-point unit is disclosed. An alignment shifter includes a shift amount calculator, a set of first level shifters and a set of second level shifter. The shift amount calculator generates one shift amount under a double-precision mode and two shift amounts under a single-precision mode. The first level shifters can concurrently receive two double-precision mantissas under the double-precision mode or two single-precision mantissas under the single-precision mode. The first level of shifts performs small shifts concurrently on the two double-precision mantissas according to the single shift amount, or on the two single-precision mantissas according to the two shift amounts. The second level shifters performs large shifts on outputs from the first level shifters to generate one double-precision floating-point result or two single-precision floating-point results.
摘要翻译：公开了一种用于在浮点单元中进行对准移位的装置。对准移位器包括移位量计算器，一组第一电平移位器和一组第二电平移位器。移位量计算器在双精度模式下产生一个移位量，并在单精度模式下产生两个移位量。第一级移位器可以在双精度模式下同时接收两个双精度尾数，或者在单精度模式下同时接收两个单精度尾数。第一级别的换档根据单位移量在两个双精度尾数上同时执行小移动，或者根据两个移位量在两个单精度尾数上同时进行。第二电平移位器对来自第一电平移位器的输出执行大的移位，以产生一个双精度浮点运算或两个单精度浮点运算结果。

2. 发明申请

US20060248423A1 Method and apparatus to disable compaction of test responses in deterministic test-set embedding-based BIST 有权
标题翻译：在确定性测试集嵌入式BIST中禁用测试响应压缩的方法和装置
公开(公告)号：US20060248423A1
公开(公告)日：2006-11-02
申请号：US11115606
申请日：2005-04-27
申请人： Shivakumar Swaminathan
发明人： Shivakumar Swaminathan
IPC分类号： G01R31/28
CPC分类号： G01R31/31813 , G01R31/318547
摘要： A method and system for built-in self-testing for high-performance circuits, configured to generate and apply a test pattern to a circuit under test (CUT). A logic structure in communication with the CUT and a memory device generates a plurality of test seeds from a plurality of original test seeds, the generated test seeds and original test seeds defining a total test seed plurality and a subset deterministic test pattern plurality. A response suppression circuit suppresses test responses from the CUT if not generated responsive to a deterministic test seed of the deterministic test pattern plurality.
摘要翻译：一种用于高性能电路的内置自检的方法和系统，用于生成测试图案并将其应用于被测电路（CUT）。与CUT和存储设备通信的逻辑结构从多个原始测试种子生成多个测试种子，生成的测试种子和原始测试种子定义总测试种子多个和子集确定性测试模式多个。响应抑制电路抑制来自CUT的测试响应，如果不是响应于确定性测试模式多个的确定性测试种子而产生的。

3. 发明授权

US07260760B2 Method and apparatus to disable compaction of test responses in deterministic test-set embedding-based BIST 有权
标题翻译：在确定性测试集嵌入式BIST中禁用测试响应压缩的方法和装置
公开(公告)号：US07260760B2
公开(公告)日：2007-08-21
申请号：US11115606
申请日：2005-04-27
申请人： Shivakumar Swaminathan
发明人： Shivakumar Swaminathan
IPC分类号： G01R31/28
CPC分类号： G01R31/31813 , G01R31/318547
摘要： A method and system for built-in self-testing for high-performance circuits, configured to generate and apply a test pattern to a circuit under test (CUT). A logic structure in communication with the CUT and a memory device generates a plurality of test seeds from a plurality of original test seeds, the generated test seeds and original test seeds defining a total test seed plurality and a subset deterministic test pattern plurality. A response suppression circuit suppresses test responses from the CUT if not generated responsive to a deterministic test seed of the deterministic test pattern plurality.
摘要翻译：一种用于高性能电路的内置自检的方法和系统，用于生成测试图案并将其应用于被测电路（CUT）。与CUT和存储设备通信的逻辑结构从多个原始测试种子生成多个测试种子，生成的测试种子和原始测试种子定义总测试种子多个和子集确定性测试模式多个。响应抑制电路抑制来自CUT的测试响应，如果不是响应于确定性测试模式多个的确定性测试种子而产生的。

4. 发明授权

US07228478B2 Built-in self-test (BIST) for high performance circuits 有权
标题翻译：内置自测（BIST）高性能电路
公开(公告)号：US07228478B2
公开(公告)日：2007-06-05
申请号：US10915981
申请日：2004-08-11
申请人： Shivakumar Swaminathan
发明人： Shivakumar Swaminathan
IPC分类号： G01R31/3183 , G01R31/3185
CPC分类号： G01R31/318555 , G01R31/318547
摘要： Test patterns for testing electrical circuits are generated by a MUX having its output operatively coupled to a Scan-In shift register and inputs receiving seed pattern signals, response signal from a response shift register, positive and negative signals from the Scan-In register. A control logic circuit provides control signals that enable the MUX to select appropriate input signals. The circuit arrangement enables relatively few seed patterns to generate relatively large number of test patterns. The seed patterns are a sub-set of a test pattern set preferably generated by software such as the Automatic Test Pattern Generator (ATPG). A method to generate the seed patterns is, also, provided.
摘要翻译：用于测试电路的测试模式由具有可操作地耦合到扫描输入移位寄存器的输出的MUX产生，并输入接收种子图形信号，来自响应移位寄存器的响应信号，来自扫描输入寄存器的正和负信号。控制逻辑电路提供使MUX能够选择合适的输入信号的控制信号。电路布置使得相对较少的种子图案能够产生相对大量的测试图案。种子图案是优选地由诸如自动测试图案生成器（ATPG）的软件生成的测试图案集的子集。也提供了生成种子模式的方法。

5. 发明申请

US20070011222A1 Floating-point processor for processing single-precision numbers 审中-公开
标题翻译：用于处理单精度数字的浮点处理器
公开(公告)号：US20070011222A1
公开(公告)日：2007-01-11
申请号：US11178073
申请日：2005-07-07
申请人： Sherman Dance , Jeffrey Summers , Shivakumar Swaminathan
发明人： Sherman Dance , Jeffrey Summers , Shivakumar Swaminathan
IPC分类号： G06F7/00
CPC分类号： G06F7/4876 , G06F2207/382
摘要： A system and method for processing single-precision floating-point numbers. The system includes a processor that has a double-precision (DP) register, wherein the DP register receives a plurality of single-precision (SP) operands, and a recoder coupled to the DP register, wherein the recoder recodes a first SP operand of the plurality of SP operands. The processor also includes a plurality of partial product (PP) units coupled to the DP register, wherein each PP unit of the plurality of PP units processes a second SP operand of the plurality of SP operands.
摘要翻译：用于处理单精度浮点数的系统和方法。该系统包括具有双精度（DP）寄存器的处理器，其中DP寄存器接收多个单精度（SP）操作数，以及耦合到DP寄存器的再编码器，其中，所述重新编码器重新编码第多个SP操作数。处理器还包括耦合到DP寄存器的多个部分乘积（PP）单元，其中多个PP单元中的每个PP单元处理多个SP操作数的第二SP操作数。

6. 发明申请

US20070283204A1 METHOD AND SYSTEM FOR DETERMINISTIC BIST 审中-公开
标题翻译：确定性方法和系统
公开(公告)号：US20070283204A1
公开(公告)日：2007-12-06
申请号：US11770013
申请日：2007-06-28
申请人： Shivakumar Swaminathan
发明人： Shivakumar Swaminathan
IPC分类号： G01R31/3177 , G01R31/3183 , G01R31/3187
CPC分类号： G01R31/31813 , G01R31/318547
摘要： Methods, systems and articles of manufactures are provided for built-in self-testing of high-performance circuits configured to generate and apply test patterns to a circuit under test (CUT). A logic structure in communication with the CUT and a memory device generates a plurality of test patterns from original test seeds, wherein a response suppression circuit suppresses CUT test responses not generated responsive to a deterministic test pattern of the test pattern plurality prior to compacting a remainder of test pattern responses not suppressed. In one aspect a logic twist counter, a logic shift counter and a logic seed counter are used to generate the test patterns with a seed generation algorithm, determine a subset deterministic test pattern plurality from the original test seeds by looping the original seeds through an input scan register, and suppress responses.
摘要翻译：提供了制造商的方法，系统和制品，用于内置自动测试的高性能电路，用于生成和应用测试图案到被测电路（CUT）。与CUT和存储装置通信的逻辑结构从原始测试种子生成多个测试模式，其中响应抑制电路抑制在压缩余数之前响应于多个测试模式的确定性测试模式而不产生的CUT测试响应的测试模式响应不被抑制。在一个方面，使用逻辑扭转计数器，逻辑移位计数器和逻辑种子计数器来生成具有种子生成算法的测试模式，通过将原始种子循环通过输入来确定来自原始测试种子的多个子集确定性测试模式扫描寄存器，并抑制响应。

7. 发明申请

US20070043795A1 Method and apparatus for performing alignment shifting in a floating-point unit 有权
标题翻译：用于在浮点单元中执行对准移位的方法和装置
公开(公告)号：US20070043795A1
公开(公告)日：2007-02-22
申请号：US11205987
申请日：2005-08-16
申请人： Sherman Dance , Jeffrey Summers , Shivakumar Swaminathan
发明人： Sherman Dance , Jeffrey Summers , Shivakumar Swaminathan
IPC分类号： G06F7/00
CPC分类号： G06F5/01
摘要： An apparatus for performing alignment shifting in a floating-point unit is disclosed. An alignment shifter includes a shift amount calculator, a set of first level shifters and a set of second level shifter. The shift amount calculator generates one shift amount under a double-precision mode and two shift amounts under a single-precision mode. The first level shifters can concurrently receive two double-precision mantissas under the double-precision mode or two single-precision mantissas under the single-precision mode. The first level of shifts performs small shifts concurrently on the two double-precision mantissas according to the single shift amount, or on the two single-precision mantissas according to the two shift amounts. The second level shifters performs large shifts on outputs from the first level shifters to generate one double-precision floating-point result or two single-precision floating-point results.
摘要翻译：公开了一种用于在浮点单元中进行对准移位的装置。对准移位器包括移位量计算器，一组第一电平移位器和一组第二电平移位器。移位量计算器在双精度模式下产生一个移位量，并在单精度模式下产生两个移位量。第一级移位器可以在双精度模式下同时接收两个双精度尾数，或者在单精度模式下同时接收两个单精度尾数。第一级别的换档根据单位移量在两个双精度尾数上同时执行小移动，或者根据两个移位量在两个单精度尾数上同时进行。第二电平移位器对来自第一电平移位器的输出执行大的移位，以产生一个双精度浮点运算或两个单精度浮点运算结果。

8. 发明申请

US20060036920A1 Built-in self-test (BIST) for high performance circuits 有权
标题翻译：内置自测（BIST）高性能电路
公开(公告)号：US20060036920A1
公开(公告)日：2006-02-16
申请号：US10915981
申请日：2004-08-11
申请人： Shivakumar Swaminathan
发明人： Shivakumar Swaminathan
IPC分类号： G01R31/28
CPC分类号： G01R31/318555 , G01R31/318547
摘要： Test patterns for testing electrical circuits are generated by a MUX having its output operatively coupled to a Scan-In shift register and inputs receiving seed pattern signals, response signal from a response shift register, positive and negative signals from the Scan-In register. A control logic circuit provides control signals that enable the MUX to select appropriate input signals. The circuit arrangement enables relatively few seed patterns to generate relatively large number of test patterns. The seed patterns are a sub-set of a test pattern set preferably generated by software such as the Automatic Test Pattern Generator (ATPG). A method to generate the seed patterns is, also, provided.
摘要翻译：用于测试电路的测试模式由具有可操作地耦合到扫描输入移位寄存器的输出的MUX产生，并输入接收种子图形信号，来自响应移位寄存器的响应信号，来自扫描输入寄存器的正和负信号。控制逻辑电路提供使MUX能够选择合适的输入信号的控制信号。电路布置使得相对较少的种子图案能够产生相对大量的测试图案。种子图案是优选地由诸如自动测试图案生成器（ATPG）的软件生成的测试图案集的子集。也提供了生成种子模式的方法。

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