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1. 发明授权

US08686423B2 Thin film transistor substrate and manufacturing method thereof 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US08686423B2
公开(公告)日：2014-04-01
申请号：US13604082
申请日：2012-09-05
申请人： Sung-Ryul Kim , Jean-Ho Song , Jae-Hyoung Youn , O-Sung Seo , Byeong-Beom Kim , Je-Hyeong Park , Jong-In Kim , Jae-Jin Song
发明人： Sung-Ryul Kim , Jean-Ho Song , Jae-Hyoung Youn , O-Sung Seo , Byeong-Beom Kim , Je-Hyeong Park , Jong-In Kim , Jae-Jin Song
IPC分类号： H01L31/00
CPC分类号： H01L29/78603 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L29/66765
摘要： A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.
摘要翻译：根据本发明的示例性实施例的薄膜晶体管阵列面板包括基板，形成在基板上的栅极线，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上的半导体层，以及数据其中所述数据线包括下数据层，上数据层，数据氧化层和缓冲层，其中所述上数据层和所述缓冲层包括相同的材料。

2. 发明申请

US20130001567A1 THIN FILM TRANSISTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US20130001567A1
公开(公告)日：2013-01-03
申请号：US13604082
申请日：2012-09-05
申请人： Sung-Ryul KIM , Jean-Ho Song , Jae-Hyoung Youn , O-Sung Seo , Byeong-Beom Kim , Je-Hyeong Park , Jong-In Kim , Jae-Jin Song
发明人： Sung-Ryul KIM , Jean-Ho Song , Jae-Hyoung Youn , O-Sung Seo , Byeong-Beom Kim , Je-Hyeong Park , Jong-In Kim , Jae-Jin Song
IPC分类号： H01L33/08
CPC分类号： H01L29/78603 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L29/66765
摘要： A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.
摘要翻译：根据本发明的示例性实施例的薄膜晶体管阵列面板包括基板，形成在基板上的栅极线，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上的半导体层，以及数据其中所述数据线包括下数据层，上数据层，数据氧化层和缓冲层，其中所述上数据层和所述缓冲层包括相同的材料。

3. 发明授权

US08304299B2 Thin film transistor substrate and manufacturing method thereof 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US08304299B2
公开(公告)日：2012-11-06
申请号：US12821668
申请日：2010-06-23
申请人： Sung-Ryul Kim , Jean-Ho Song , Jae-Hyoung Youn , O-Sung Seo , Byeong-Beom Kim , Je-Hyeong Park , Jong-In Kim , Jae-Jin Song
发明人： Sung-Ryul Kim , Jean-Ho Song , Jae-Hyoung Youn , O-Sung Seo , Byeong-Beom Kim , Je-Hyeong Park , Jong-In Kim , Jae-Jin Song
IPC分类号： H01L21/00
CPC分类号： H01L29/78603 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L29/66765
摘要： A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.
摘要翻译：根据本发明的示例性实施例的薄膜晶体管阵列面板包括基板，形成在基板上的栅极线，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上的半导体层，以及数据其中所述数据线包括下数据层，上数据层，数据氧化层和缓冲层，其中所述上数据层和所述缓冲层包括相同的材料。

4. 发明申请

US20110108839A1 Thin Film Transistor Substrate and Manufacturing Method Thereof 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US20110108839A1
公开(公告)日：2011-05-12
申请号：US12821668
申请日：2010-06-23
申请人： Sung-Ryul Kim , Jean-Ho Song , Jae-Hyoung Youn , O-Sung Seo , Byeong-Beom Kim , Je-Hyeong Park , Jong-In Kim , Jae-Jin Song
发明人： Sung-Ryul Kim , Jean-Ho Song , Jae-Hyoung Youn , O-Sung Seo , Byeong-Beom Kim , Je-Hyeong Park , Jong-In Kim , Jae-Jin Song
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/78603 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L29/66765
摘要： A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.
摘要翻译：根据本发明的示例性实施例的薄膜晶体管阵列面板包括基板，形成在基板上的栅极线，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上的半导体层，以及数据其中所述数据线包括下数据层，上数据层，数据氧化层和缓冲层，其中所述上数据层和所述缓冲层包括相同的材料。

5. 发明授权

US08865528B2 Thin film transistor substrate and the method thereof 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US08865528B2
公开(公告)日：2014-10-21
申请号：US12844356
申请日：2010-07-27
申请人： Jean-Ho Song , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
发明人： Jean-Ho Song , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L27/124 , H01L27/12 , H01L27/1214 , H01L27/1288 , H01L29/42368 , H01L29/458 , H01L29/78669
摘要： A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
摘要翻译：薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。栅极绝缘层可以具有台阶形状。

6. 发明申请

US20110133193A1 THIN FILM TRANSISTOR SUBSTRATE AND THE METHOD THEREOF 有权
标题翻译：薄膜晶体管基板及其方法
公开(公告)号：US20110133193A1
公开(公告)日：2011-06-09
申请号：US12844356
申请日：2010-07-27
申请人： Jean-Ho SONG , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
发明人： Jean-Ho SONG , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
IPC分类号： H01L27/12 , H01L29/786 , H01L21/336
CPC分类号： H01L27/124 , H01L27/12 , H01L27/1214 , H01L27/1288 , H01L29/42368 , H01L29/458 , H01L29/78669
摘要： A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
摘要翻译：薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。栅极绝缘层可以具有台阶形状。

7. 发明申请

US20110037070A1 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20110037070A1
公开(公告)日：2011-02-17
申请号：US12820461
申请日：2010-06-22
申请人： SUNG-RYUL KIM , Hyeong-Suk Yoo , Byeong-Hoo Cho , O-Sung Seo , Seong-Hun Kim
发明人： SUNG-RYUL KIM , Hyeong-Suk Yoo , Byeong-Hoo Cho , O-Sung Seo , Seong-Hun Kim
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/42384 , H01L29/4908
摘要： A thin film transistor substrate includes a substrate including a display area and a peripheral area surrounding the display area, gate lines formed on the substrate including gate electrodes, an auxiliary insulating layer formed on the gate lines, a gate insulating layer formed on the auxiliary insulating layer and the gate lines, a semiconductor layer formed on the gate insulating layer, data lines formed on the semiconductor layer including source electrodes and drain electrodes, a passivation layer formed on the data lines, pixel electrodes formed on the passivation layer and electrically connected to the drain electrode, wherein the boundary line of the auxiliary insulating layer is located at or within the boundary of the gate line.
摘要翻译：薄膜晶体管基板包括包括显示区域和围绕显示区域的外围区域的基板，形成在包括栅电极的基板上的栅极线，形成在栅极线上的辅助绝缘层，形成在辅助绝缘层上的栅极绝缘层形成在栅极绝缘层上的半导体层，形成在包括源电极和漏电极的半导体层上的数据线，形成在数据线上的钝化层，形成在钝化层上的电连接到所述漏电极，其中所述辅助绝缘层的边界线位于所述栅极线的边界处或所述栅极线的边界内。

8. 发明申请

US20100270552A1 THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US20100270552A1
公开(公告)日：2010-10-28
申请号：US12571323
申请日：2009-09-30
申请人： Ki-Yong Song , Sung-Haeng Cho , Jae-Hong Kim , Sung-Hen Cho , Yong-Mo Choi , Hyung-Jun Kim , Sung-Ryul Kim , Byeong-Hoon Cho , O-Sung Seo , Seong-Hun Kim
发明人： Ki-Yong Song , Sung-Haeng Cho , Jae-Hong Kim , Sung-Hen Cho , Yong-Mo Choi , Hyung-Jun Kim , Sung-Ryul Kim , Byeong-Hoon Cho , O-Sung Seo , Seong-Hun Kim
IPC分类号： H01L33/00 , B32B37/00 , C23F1/00
CPC分类号： C23C18/1608 , C23C18/31 , H01L21/0271 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/458 , Y10T156/10
摘要： A protrusion of dry-etched pattern of a thin film transistor substrate generated due to a difference between isotropy of wet etching and anisotropy of dry etching is removed by forming a plating part on a surface of the wet etched pattern through an electroless plating method. If the plating part is formed on a data pattern layer of the substrate, the width or the thickness of the data pattern layer may be increased without loss of aperture ratio, the channel length of the semiconductor layer may be reduced under the limit according to the stepper resolution and the protrusion part of the semiconductor layer may be removed. As a result, the aperture ratio may be increased, the resistance may be reduced, and the driving margin may be increased due to rising of the ion current. Furthermore, the so-called water-fall noise phenomenon may be eliminated.
摘要翻译：通过化学镀法在湿蚀刻图案的表面上形成电镀部分，可以消除由于湿蚀刻的各向同性和干蚀刻的各向异性而产生的薄膜晶体管基板的干蚀刻图案的突起。如果电镀部分形成在基板的数据图案层上，则数据图形层的宽度或厚度可以增加而不损失开口率，半导体层的沟道长度可以在根据可以去除步进分辨率和半导体层的突起部分。结果，可以增加开口率，可以降低电阻，并且由于离子电流的上升可能增加驱动裕度。此外，可以消除所谓的水落噪声现象。

9. 发明授权

US08476633B2 Thin film transistor array substrate for a display panel and a method for manufacturing a thin film transistor array substrate for a display panel 有权
标题翻译：用于显示面板的薄膜晶体管阵列基板和用于制造用于显示面板的薄膜晶体管阵列基板的方法
公开(公告)号：US08476633B2
公开(公告)日：2013-07-02
申请号：US12560652
申请日：2009-09-16
申请人： Hyeong-Suk Yoo , Ho-Jun Lee , Sung-ryul Kim , O-Sung Seo , Hong-Kee Chin
发明人： Hyeong-Suk Yoo , Ho-Jun Lee , Sung-ryul Kim , O-Sung Seo , Hong-Kee Chin
IPC分类号： H01L29/786
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/124 , H01L27/1248
摘要： A method of manufacturing a thin film transistor capable of simplifying a substrate structure and a manufacturing process is disclosed. The method of manufacturing a thin film transistor array substrate comprising a three mask process. The 3 mask process comprising, forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming a first, second, and third passivation film successively on the substrate. Over the above multi-layers of the passivation film forming a first photoresist pattern comprising a first portion formed on part of the drain electrode and on the pixel region, and a second portion wherein, the second portion thicker than the first portion, and then patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern; and forming a transparent electrode pattern on the second passivation layer.
摘要翻译：公开了一种能够简化衬底结构和制造工艺的制造薄膜晶体管的方法。制造包括三掩模工艺的薄膜晶体管阵列基板的方法。 3掩模工艺包括：在衬底上形成栅极图案，在衬底上形成栅极绝缘膜，在衬底上形成源极/漏极图案和半导体图案，在第一，第二和第三钝化膜上依次形成第一，第二和第三钝化膜基质。在上述多层钝化膜上形成第一光致抗蚀剂图案，该第一光致抗蚀剂图案包括形成在漏电极的一部分上和在像素区域上的第一部分，以及第二部分，其中第二部分比第一部分厚，使用第一光致抗蚀剂图案的第三钝化膜，通过去除第一光致抗蚀剂图案的第一部分形成第二光致抗蚀剂图案，在基板上形成透明电极膜，去除第二光致抗蚀剂图案和设置在第二光致抗蚀剂上的透明电极膜模式; 以及在所述第二钝化层上形成透明电极图案。

10. 发明授权

US07847291B2 Display substrate 有权
标题翻译：显示基板
公开(公告)号：US07847291B2
公开(公告)日：2010-12-07
申请号：US12486328
申请日：2009-06-17
申请人： Kap-Soo Yoon , Sung-Hoon Yang , Sung-Ryul Kim , O-Sung Seo , Hwa-Yeul Oh , Jae-Ho Choi , Seong-Hun Kim , Yong-Mo Choi
发明人： Kap-Soo Yoon , Sung-Hoon Yang , Sung-Ryul Kim , O-Sung Seo , Hwa-Yeul Oh , Jae-Ho Choi , Seong-Hun Kim , Yong-Mo Choi
IPC分类号： H01L29/04
CPC分类号： H01L27/12 , H01L27/1225 , H01L29/7869
摘要： A display substrate includes; a substrate, a gate electrode arranged on the substrate, a semiconductor pattern arranged on the gate electrode, a source electrode arranged on the semiconductor pattern, a drain electrode arranged on the semiconductor pattern and spaced apart from the source electrode, an insulating layer arranged on, and substantially covering, the source electrode and the drain electrode to cover the source electrode and the drain electrode, a conductive layer pattern arranged on the insulating layer and overlapped aligned with the semiconductor pattern, a pixel electrode electrically connected to the drain electrode, and a storage electrode arranged on the substrate and overlapped overlapping with the pixel electrode, the storage electrode being electrically connected to the conductive layer pattern.
摘要翻译：显示基板包括：衬底，布置在衬底上的栅电极，布置在栅电极上的半导体图案，布置在半导体图案上的源电极，布置在半导体图案上并与源电极间隔开的漏电极，布置在并且基本上覆盖源电极和漏极以覆盖源电极和漏电极，布置在绝缘层上并与半导体图案重叠的导电层图案，与漏电极电连接的像素电极，以及存储电极，设置在所述基板上，与所述像素电极重叠地重叠，所述存储电极与所述导电层图案电连接。

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