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1. 发明申请

US20120273787A1 THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20120273787A1
公开(公告)日：2012-11-01
申请号：US13244086
申请日：2011-09-23
申请人： Hwa Yeul OH , O Sung Seo , Je Hyeong Park , Shin II Choi , Dong-Won Woo , Ji-Young Park , Jean Ho Song , Sang Gab Kim
发明人： Hwa Yeul OH , O Sung Seo , Je Hyeong Park , Shin II Choi , Dong-Won Woo , Ji-Young Park , Jean Ho Song , Sang Gab Kim
IPC分类号： H01L33/08 , H01L21/336
CPC分类号： H01L27/1259 , G02F1/136286
摘要： In a thin film transistor array panel according to an exemplary embodiment of the present invention, a plasma process using a mixed gas including hydrogen gas and nitrogen gas with a ratio of a predetermined value is undertaken before depositing a passivation layer. In this manner, performance deterioration of the thin film transistor may be prevented and simultaneously, haze in a transparent electrode may be prevented. Alternatively, a first passivation layer is depsoited, then removed. A passivation layer is again re-deposited, such that little or no haze is present in the resulting passivation layer.
摘要翻译：在根据本发明的示例性实施例的薄膜晶体管阵列面板中，在沉积钝化层之前进行使用包括氢气和含有预定值的氮气的混合气体的等离子体处理。以这种方式，可以防止薄膜晶体管的性能恶化，并且同时可以防止透明电极中的雾度。或者，第一钝化层被剥离，然后除去。再次沉积钝化层，使得在所得钝化层中存在很少或没有雾度。

2. 发明申请

US20120135555A1 METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL 有权
标题翻译：制造薄膜晶体管阵列的方法
公开(公告)号：US20120135555A1
公开(公告)日：2012-05-31
申请号：US13157806
申请日：2011-06-10
申请人： Jong-Hyun CHOUNG , Yang Ho BAE , Jean Ho SONG , O. Sung SEO , Sun-Young HONG , Hwa Yeul OH , Bong-Kyun KIM , Nam Seok SUH , Dong-Ju YANG , Wang Woo LEE
发明人： Jong-Hyun CHOUNG , Yang Ho BAE , Jean Ho SONG , O. Sung SEO , Sun-Young HONG , Hwa Yeul OH , Bong-Kyun KIM , Nam Seok SUH , Dong-Ju YANG , Wang Woo LEE
IPC分类号： H01L33/62
CPC分类号： H01L21/32134 , G02F1/136227 , H01L27/1288 , H01L29/41733
摘要： A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.
摘要翻译：一种制造薄膜晶体管阵列面板的方法，包括：在栅绝缘层和栅极线上依次形成第一硅层，第二硅层，下金属层和上金属层; 在上金属层上形成第一膜图案; 通过蚀刻上金属层和下金属层，形成第一下金属图案和包括突起的第一上金属图案; 通过蚀刻第一和第二硅层形成第一和第二硅图案; 通过灰化第一膜图案形成第二膜图案; 通过蚀刻第一上金属图案形成第二上金属图案; 通过蚀刻第一下金属图案和第一和第二硅图案来形成数据线和薄膜晶体管; 并在所得物上形成钝化层和像素电极。

3. 发明申请

US20110037070A1 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20110037070A1
公开(公告)日：2011-02-17
申请号：US12820461
申请日：2010-06-22
申请人： SUNG-RYUL KIM , Hyeong-Suk Yoo , Byeong-Hoo Cho , O-Sung Seo , Seong-Hun Kim
发明人： SUNG-RYUL KIM , Hyeong-Suk Yoo , Byeong-Hoo Cho , O-Sung Seo , Seong-Hun Kim
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/42384 , H01L29/4908
摘要： A thin film transistor substrate includes a substrate including a display area and a peripheral area surrounding the display area, gate lines formed on the substrate including gate electrodes, an auxiliary insulating layer formed on the gate lines, a gate insulating layer formed on the auxiliary insulating layer and the gate lines, a semiconductor layer formed on the gate insulating layer, data lines formed on the semiconductor layer including source electrodes and drain electrodes, a passivation layer formed on the data lines, pixel electrodes formed on the passivation layer and electrically connected to the drain electrode, wherein the boundary line of the auxiliary insulating layer is located at or within the boundary of the gate line.
摘要翻译：薄膜晶体管基板包括包括显示区域和围绕显示区域的外围区域的基板，形成在包括栅电极的基板上的栅极线，形成在栅极线上的辅助绝缘层，形成在辅助绝缘层上的栅极绝缘层形成在栅极绝缘层上的半导体层，形成在包括源电极和漏电极的半导体层上的数据线，形成在数据线上的钝化层，形成在钝化层上的电连接到所述漏电极，其中所述辅助绝缘层的边界线位于所述栅极线的边界处或所述栅极线的边界内。

4. 发明申请

US20100270552A1 THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US20100270552A1
公开(公告)日：2010-10-28
申请号：US12571323
申请日：2009-09-30
申请人： Ki-Yong Song , Sung-Haeng Cho , Jae-Hong Kim , Sung-Hen Cho , Yong-Mo Choi , Hyung-Jun Kim , Sung-Ryul Kim , Byeong-Hoon Cho , O-Sung Seo , Seong-Hun Kim
发明人： Ki-Yong Song , Sung-Haeng Cho , Jae-Hong Kim , Sung-Hen Cho , Yong-Mo Choi , Hyung-Jun Kim , Sung-Ryul Kim , Byeong-Hoon Cho , O-Sung Seo , Seong-Hun Kim
IPC分类号： H01L33/00 , B32B37/00 , C23F1/00
CPC分类号： C23C18/1608 , C23C18/31 , H01L21/0271 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/458 , Y10T156/10
摘要： A protrusion of dry-etched pattern of a thin film transistor substrate generated due to a difference between isotropy of wet etching and anisotropy of dry etching is removed by forming a plating part on a surface of the wet etched pattern through an electroless plating method. If the plating part is formed on a data pattern layer of the substrate, the width or the thickness of the data pattern layer may be increased without loss of aperture ratio, the channel length of the semiconductor layer may be reduced under the limit according to the stepper resolution and the protrusion part of the semiconductor layer may be removed. As a result, the aperture ratio may be increased, the resistance may be reduced, and the driving margin may be increased due to rising of the ion current. Furthermore, the so-called water-fall noise phenomenon may be eliminated.
摘要翻译：通过化学镀法在湿蚀刻图案的表面上形成电镀部分，可以消除由于湿蚀刻的各向同性和干蚀刻的各向异性而产生的薄膜晶体管基板的干蚀刻图案的突起。如果电镀部分形成在基板的数据图案层上，则数据图形层的宽度或厚度可以增加而不损失开口率，半导体层的沟道长度可以在根据可以去除步进分辨率和半导体层的突起部分。结果，可以增加开口率，可以降低电阻，并且由于离子电流的上升可能增加驱动裕度。此外，可以消除所谓的水落噪声现象。

5. 发明授权

US08823005B2 Thin-film transistor and method of manufacturing the same 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US08823005B2
公开(公告)日：2014-09-02
申请号：US13167668
申请日：2011-06-23
申请人： O-Sung Seo , Seong-Hun Kim , Yang-Ho Bae , Jean-Ho Song
发明人： O-Sung Seo , Seong-Hun Kim , Yang-Ho Bae , Jean-Ho Song
IPC分类号： H01L29/66 , H01L29/45 , H01L29/786
CPC分类号： H01L29/78618 , H01L29/458 , H01L29/66765
摘要： A thin-film transistor (TFT) and a method of manufacturing the same are disclosed herein. The TFT may include a gate electrode disposed on an insulating substrate, an insulating layer disposed on the insulating substrate and the gate electrode, an active layer pattern disposed on the insulating layer to overlap the gate electrode, a source electrode disposed on the insulating layer and at least part of which overlaps the active layer pattern, and a drain electrode which is separated from the source electrode and at least part of which overlaps the active layer pattern. A first ohmic contact layer pattern may be disposed between the active layer pattern and the source electrode and between the active layer pattern and the drain electrode. The first ohmic contact layer may have higher nitrogen content on its surface than in other portions of the first ohmic contact layer.
摘要翻译：本文公开了一种薄膜晶体管（TFT）及其制造方法。 TFT可以包括设置在绝缘基板上的栅电极，设置在绝缘基板上的绝缘层和栅电极，设置在绝缘层上的与栅电极重叠的有源层图案，设置在绝缘层上的源电极和其至少一部分与有源层图案重叠，以及与源电极分离并且其至少一部分与有源层图案重叠的漏电极。可以在有源层图案和源电极之间以及有源层图案和漏电极之间设置第一欧姆接触层图案。第一欧姆接触层在其表面上可以具有比在第一欧姆接触层的其它部分更高的氮含量。

6. 发明授权

US08686423B2 Thin film transistor substrate and manufacturing method thereof 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US08686423B2
公开(公告)日：2014-04-01
申请号：US13604082
申请日：2012-09-05
申请人： Sung-Ryul Kim , Jean-Ho Song , Jae-Hyoung Youn , O-Sung Seo , Byeong-Beom Kim , Je-Hyeong Park , Jong-In Kim , Jae-Jin Song
发明人： Sung-Ryul Kim , Jean-Ho Song , Jae-Hyoung Youn , O-Sung Seo , Byeong-Beom Kim , Je-Hyeong Park , Jong-In Kim , Jae-Jin Song
IPC分类号： H01L31/00
CPC分类号： H01L29/78603 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L29/66765
摘要： A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.
摘要翻译：根据本发明的示例性实施例的薄膜晶体管阵列面板包括基板，形成在基板上的栅极线，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上的半导体层，以及数据其中所述数据线包括下数据层，上数据层，数据氧化层和缓冲层，其中所述上数据层和所述缓冲层包括相同的材料。

7. 发明申请

US20130234144A1 DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：显示基板及其制造方法
公开(公告)号：US20130234144A1
公开(公告)日：2013-09-12
申请号：US13565639
申请日：2012-08-02
申请人： O-Sung SEO , Hwa-Yeul OH , Hyoung-Cheol LEE , Tae-Kyung YIM
发明人： O-Sung SEO , Hwa-Yeul OH , Hyoung-Cheol LEE , Tae-Kyung YIM
IPC分类号： H01L27/15 , H01L33/08
CPC分类号： H01L27/124 , H01L27/3272 , H01L27/3279 , H01L29/78633
摘要： RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line.
摘要翻译：通过在栅极线中使用低电阻率导体和用于形成对应的栅电极的不同导体来减小宽显示器的栅极线中的RC延迟。更具体地，对应的显示基板包括由第一栅极线金属制成的栅极线，由第一数据线金属制成的数据线，像素晶体管和第一连接提供部。像素晶体管包括由多晶硅（poly-Si）形成的第一有源图案和形成在其上方并由不同于第一栅极线金属的导电材料制成的第一栅电极。第一连接提供部分将第一栅电极连接到栅极线。另一方面，源电极从数据线整体延伸。

8. 发明授权

US08198657B2 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08198657B2
公开(公告)日：2012-06-12
申请号：US12652379
申请日：2010-01-05
申请人： Dong-Hoon Lee , Do-Hyun Kim , Chang-Oh Jeong , O-Sung Seo , Xin-Xing Li
发明人： Dong-Hoon Lee , Do-Hyun Kim , Chang-Oh Jeong , O-Sung Seo , Xin-Xing Li
IPC分类号： H01L23/52 , H01L21/82
CPC分类号： H01L27/124 , H01L29/78618
摘要： A thin film transistor array panel includes an insulating substrate. A gate line is formed on the insulating substrate and has a gate electrode. A gate insulating layer is formed on the gate line. A semiconductor layer is formed on the gate insulating layer and overlaps the gate electrode. Diffusion barriers are formed on the semiconductor layer and contain nitrogen. A data line crosses the gate line and has a source electrode partially contacting the diffusion barriers and a drain electrode partially contacting the diffusion barriers and facing the source electrode. The drain electrode is on the gate electrode. A pixel electrode is electrically connected to the drain electrode.
摘要翻译：薄膜晶体管阵列面板包括绝缘基板。在绝缘基板上形成栅极线，并具有栅电极。在栅极线上形成栅绝缘层。半导体层形成在栅极绝缘层上并与栅电极重叠。在半导体层上形成扩散阻挡层并含有氮。数据线与栅极线交叉，并且具有部分地接触扩散阻挡层的源电极和部分地接触扩散阻挡层并面向源电极的漏电极。漏电极在栅电极上。像素电极电连接到漏电极。

9. 发明授权

US08557621B2 Method for manufacturing thin film transistor array panel 有权
标题翻译：制造薄膜晶体管阵列面板的方法
公开(公告)号：US08557621B2
公开(公告)日：2013-10-15
申请号：US13157806
申请日：2011-06-10
申请人： Jong-Hyun Choung , Yang Ho Bae , Jean Ho Song , O Sung Seo , Sun-Young Hong , Hwa Yeul Oh , Bong-Kyun Kim , Nam Seok Suh , Dong-Ju Yang , Wang Woo Lee
发明人： Jong-Hyun Choung , Yang Ho Bae , Jean Ho Song , O Sung Seo , Sun-Young Hong , Hwa Yeul Oh , Bong-Kyun Kim , Nam Seok Suh , Dong-Ju Yang , Wang Woo Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/32134 , G02F1/136227 , H01L27/1288 , H01L29/41733
摘要： A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.
摘要翻译：一种制造薄膜晶体管阵列面板的方法，包括：在栅绝缘层和栅极线上依次形成第一硅层，第二硅层，下金属层和上金属层; 在上金属层上形成第一膜图案; 通过蚀刻上金属层和下金属层，形成第一下金属图案和包括突起的第一上金属图案; 通过蚀刻第一和第二硅层形成第一和第二硅图案; 通过灰化第一膜图案形成第二膜图案; 通过蚀刻第一上金属图案形成第二上金属图案; 通过蚀刻第一下金属图案和第一和第二硅图案来形成数据线和薄膜晶体管; 并在所得物上形成钝化层和像素电极。

10. 发明授权

US08476633B2 Thin film transistor array substrate for a display panel and a method for manufacturing a thin film transistor array substrate for a display panel 有权
标题翻译：用于显示面板的薄膜晶体管阵列基板和用于制造用于显示面板的薄膜晶体管阵列基板的方法
公开(公告)号：US08476633B2
公开(公告)日：2013-07-02
申请号：US12560652
申请日：2009-09-16
申请人： Hyeong-Suk Yoo , Ho-Jun Lee , Sung-ryul Kim , O-Sung Seo , Hong-Kee Chin
发明人： Hyeong-Suk Yoo , Ho-Jun Lee , Sung-ryul Kim , O-Sung Seo , Hong-Kee Chin
IPC分类号： H01L29/786
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/124 , H01L27/1248
摘要： A method of manufacturing a thin film transistor capable of simplifying a substrate structure and a manufacturing process is disclosed. The method of manufacturing a thin film transistor array substrate comprising a three mask process. The 3 mask process comprising, forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming a first, second, and third passivation film successively on the substrate. Over the above multi-layers of the passivation film forming a first photoresist pattern comprising a first portion formed on part of the drain electrode and on the pixel region, and a second portion wherein, the second portion thicker than the first portion, and then patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern; and forming a transparent electrode pattern on the second passivation layer.
摘要翻译：公开了一种能够简化衬底结构和制造工艺的制造薄膜晶体管的方法。制造包括三掩模工艺的薄膜晶体管阵列基板的方法。 3掩模工艺包括：在衬底上形成栅极图案，在衬底上形成栅极绝缘膜，在衬底上形成源极/漏极图案和半导体图案，在第一，第二和第三钝化膜上依次形成第一，第二和第三钝化膜基质。在上述多层钝化膜上形成第一光致抗蚀剂图案，该第一光致抗蚀剂图案包括形成在漏电极的一部分上和在像素区域上的第一部分，以及第二部分，其中第二部分比第一部分厚，使用第一光致抗蚀剂图案的第三钝化膜，通过去除第一光致抗蚀剂图案的第一部分形成第二光致抗蚀剂图案，在基板上形成透明电极膜，去除第二光致抗蚀剂图案和设置在第二光致抗蚀剂上的透明电极膜模式; 以及在所述第二钝化层上形成透明电极图案。

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