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1. 发明授权

US09343666B2 Damascene metal-insulator-metal (MIM) device with improved scaleability 有权
标题翻译：大马士革金属绝缘体金属（MIM）装置，具有改进的可扩展性
公开(公告)号：US09343666B2
公开(公告)日：2016-05-17
申请号：US13529284
申请日：2012-06-21
申请人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael Vanbuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffery A. Shields
发明人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael Vanbuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffery A. Shields
IPC分类号： H01L21/20 , H01L45/00 , H01L27/24
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
摘要： A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
摘要翻译：制造存储器件的现有方法包括以下步骤：提供电介质层，在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充物并且在开关体上设置第二导电体。在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

2. 发明授权

US08089113B2 Damascene metal-insulator-metal (MIM) device 有权
标题翻译：大马士革金属绝缘子金属（MIM）器件
公开(公告)号：US08089113B2
公开(公告)日：2012-01-03
申请号：US11633929
申请日：2006-12-05
申请人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
发明人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
IPC分类号： H01L29/94 , H01L27/108
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/146 , H01L45/1666
摘要： The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.
摘要翻译：制造存储器件的本方法包括以下步骤：提供电介质层，在电介质层中提供开口，在电介质层的开口中提供第一导电体，在开口中提供开关体，并提供第二导电体在开口处。

3. 发明申请

US20080123401A1 Damascene metal-insulator-metal (MIM) device with improved scaleability 有权
标题翻译：大马士革金属绝缘体金属（MIM）装置，具有改进的可扩展性
公开(公告)号：US20080123401A1
公开(公告)日：2008-05-29
申请号：US11521204
申请日：2006-09-14
申请人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
发明人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
IPC分类号： G11C11/34 , H01L21/44
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
摘要： A present method of fabricating a memory device includes the steps of providing a dielectric layer;, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
摘要翻译：本发明的制造存储器件的方法包括以下步骤：提供电介质层;在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充开口，并且在开关体上提供第二导电体。在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

4. 发明授权

US08232175B2 Damascene metal-insulator-metal (MIM) device with improved scaleability 有权
标题翻译：大马士革金属绝缘体金属（MIM）装置，具有改进的可扩展性
公开(公告)号：US08232175B2
公开(公告)日：2012-07-31
申请号：US11521204
申请日：2006-09-14
申请人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
发明人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
IPC分类号： H01L21/20
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
摘要： A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
摘要翻译：制造存储器件的现有方法包括以下步骤：提供电介质层，在介电层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充物并且在开关体上设置第二导电体。在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

5. 发明申请

US20080132068A1 Damascene metal-insulator-metal (MIM) device 有权
标题翻译：大马士革金属绝缘子金属（MIM）器件
公开(公告)号：US20080132068A1
公开(公告)日：2008-06-05
申请号：US11633929
申请日：2006-12-05
申请人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
发明人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
IPC分类号： H01L21/44
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/146 , H01L45/1666
摘要： The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.
摘要翻译：制造存储器件的本方法包括以下步骤：提供电介质层，在电介质层中提供开口，在电介质层的开口中提供第一导电体，在开口中提供开关体，并提供第二导电体在开口处。

6. 发明授权

US07358191B1 Method for decreasing sheet resistivity variations of an interconnect metal layer 有权
标题翻译：降低互连金属层的薄层电阻率变化的方法
公开(公告)号：US07358191B1
公开(公告)日：2008-04-15
申请号：US11388390
申请日：2006-03-24
申请人： Krishnashree Achuthan , Brad Davis , James Xie , Kashmir Sahota
发明人： Krishnashree Achuthan , Brad Davis , James Xie , Kashmir Sahota
IPC分类号： H01L21/311
CPC分类号： H01L21/3212 , H01L21/7684
摘要： According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenches such that the metal layer has a dome-shaped profile over the wafer. The method further includes performing a planarizing process to form a number of interconnect lines, where each of the interconnect lines is situated in one of the trenches. The dome-shaped profile of the metal layer causes the interconnect lines to have a reduced thickness variation across the wafer after performing the planarizing process. The interconnect lines are situated in an interconnect metal layer, where the dome-shaped profile of the metal layer causes the interconnect metal layer to have increased sheet resistivity uniformity across the wafer after performing the planarizing process.
摘要翻译：根据一个示例性实施例，一种方法包括在电介质层中形成多个沟槽的步骤，其中电介质层位于晶片之上。该方法还包括在电介质层上和沟槽中形成金属层，使得金属层在晶片上具有圆顶形轮廓。该方法还包括执行平面化处理以形成多个互连线，其中每个互连线位于沟槽中的一个中。在执行平坦化处理之后，金属层的圆顶形轮廓使得互连线在晶片上具有减小的厚度变化。互连线位于互连金属层中，其中金属层的圆顶形轮廓使得互连金属层在执行平坦化处理之后在晶片上具有增加的片电阻率均匀性。

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