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1. 发明授权

US11615040B2 Structures and methods for adjusting a reference clock based on data transmission rate between PHY and MAC layers 有权
公开(公告)号：US11615040B2
公开(公告)日：2023-03-28
申请号：US17390428
申请日：2021-07-30
申请人： Texas Instruments Incorporated
发明人： Geet Govind Modi , Sumantra Seth , Subhashish Mukherjee
IPC分类号： G06F13/20 , G06F1/08
摘要： A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

2. 发明申请

US20230035848A1 Variable Speed Data Transmission Between PHY Layer and MAC Layer 有权
公开(公告)号：US20230035848A1
公开(公告)日：2023-02-02
申请号：US17390428
申请日：2021-07-30
申请人： Texas Instruments Incorporated
发明人： Geet Govind Modi , Sumantra Seth , Subhashish Mukherjee
IPC分类号： G06F13/20 , G06F1/08
摘要： A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

3. 发明授权

US09496007B2 Method and apparatus for generating piece-wise linear regulated supply 有权
标题翻译：用于产生分段线性调节电源的方法和装置
公开(公告)号：US09496007B2
公开(公告)日：2016-11-15
申请号：US14503545
申请日：2014-10-01
申请人： Texas Instruments Incorporated
发明人： Sumantra Seth , Subrato Roy , Deepak Verma
IPC分类号： G05F1/575 , G11C5/14 , H01C1/16
CPC分类号： G11C5/147 , H01C1/16
摘要： The disclosure provides a voltage regulator for generating piece-wise linear regulated supply voltage. The voltage regulator includes a first clamp circuit that receives a reference voltage and an analog supply voltage. A second clamp circuit receives the reference voltage. A voltage divider circuit is coupled to the first clamp circuit and the second clamp circuit. The voltage divider circuit receives a peripheral supply voltage and generates a regulated supply voltage.
摘要翻译：本公开提供了用于产生分段线性稳压电源电压的电压调节器。电压调节器包括接收参考电压和模拟电源电压的第一钳位电路。第二钳位电路接收参考电压。分压器电路耦合到第一钳位电路和第二钳位电路。分压器电路接收外围电源电压并产生稳定的电源电压。

4. 发明申请

US20140247071A1 ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES 审中-公开
标题翻译：在UDSM过程中VBUS脉冲的结构
公开(公告)号：US20140247071A1
公开(公告)日：2014-09-04
申请号：US14258771
申请日：2014-04-22
申请人： Texas Instruments Incorporated
发明人： Sumantra Seth , Somasunder Kattepura Sreenath , Sujoy Chinmoy Chakravarty , Arakali Abhijith
IPC分类号： H03K3/012
CPC分类号： H03K3/012 , G06F1/26 , H02J2007/0062 , H03K19/0185
摘要： Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.
摘要翻译：用于确保USB-OTG（On Go Go）会话请求协议的Ultra Deep Sub Micron（UDSM）过程中的VBUS脉冲的架构，该体系结构是至少部署充电电路的类型，其使用连接在充电电路的前进路径。该架构可以包括二极管分压器，其包括节点并且在所述充电电路中从VBUS连接。一个实施例使用包括晶体管的充电和放电电路。充电电路晶体管可以包括PMOS晶体管，并且放电电路晶体管可以包括NMOS晶体管。该结构可以包括连接在所述VBUS和地之间的接近100K欧姆的总电阻值的三个电阻串，其中放电电路晶体管可以包括漏极延伸的NMOS晶体管。充电和放电电路晶体管具有约3.6V的VDS和VGD，由此不需要高VGS晶体管。

5. 发明授权

US11171603B2 Voltage tolerant oscillator with enhanced RF immunity performance 有权
公开(公告)号：US11171603B2
公开(公告)日：2021-11-09
申请号：US17074688
申请日：2020-10-20
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Sumantra Seth , Isha Khandelwal , Rama Santosh Neelim Kumar Kattamuri
IPC分类号： H03B5/36 , H03H7/06
摘要： An integrated circuit includes an inverter, first and second capacitors, a resistor, and a transistor. The inverter has an input and an output. The first capacitor is coupled to a ground. The transistor has a first transistor terminal, a second transistor terminal, and a control input. The first transistor terminal is coupled to the first capacitor and the second transistor terminal is coupled to the input of the inverter. The second capacitor is coupled between the output of the inverter and the ground. The resistor is coupled between the output of the inverter and the first transistor terminal.

6. 发明申请

US20140266361A1 DUTY CYCLE CORRECTION CIRCUIT 审中-公开
标题翻译：占空比校正电路
公开(公告)号：US20140266361A1
公开(公告)日：2014-09-18
申请号：US13886637
申请日：2013-05-03
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Siddharth Shashidharan , Sumantra Seth , Ravi Jithendra Mehta , Biman Chattopadhyay , Sujoy Chinmoy Chakravarty
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： In an embodiment, a duty cycle correction circuit comprises a first set of inverters connected in series, a first filter, a first feedback circuit and a second feedback circuit. A first inverter in the series is configured to receive a clock signal and a last inverter in the series is configured to provide a first output clock signal. The first filter is configured to generate a first direct current (DC) voltage signal at an output of the first filter. The first feedback circuit is configured to control a rise time of a signal transition at an output terminal of the first inverter to control a duty cycle of the first output clock cycle. The second feedback circuit is configured to control a fall time of the signal transition at the output terminal of the first inverter to control the duty cycle of the first output clock cycle.
摘要翻译：在一个实施例中，占空比校正电路包括串联连接的第一组反相器，第一滤波器，第一反馈电路和第二反馈电路。串联的第一反相器被配置为接收时钟信号，并且串联中的最后一个反相器被配置为提供第一输出时钟信号。第一滤波器被配置为在第一滤波器的输出处产生第一直流（DC）电压信号。第一反馈电路被配置为控制第一反相器的输出端处的信号转变的上升时间，以控制第一输出时钟周期的占空比。第二反馈电路被配置为控制第一反相器的输出端处的信号转变的下降时间，以控制第一输出时钟周期的占空比。

7. 发明授权

US11637529B2 Voltage tolerant oscillator with enhanced RF immunity performance 有权
公开(公告)号：US11637529B2
公开(公告)日：2023-04-25
申请号：US17495097
申请日：2021-10-06
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Sumantra Seth , Isha Khandelwal , Rama Santosh Neelim Kumar Kattamuri
IPC分类号： H03B5/36 , H03H7/06
摘要： An integrated circuit includes an inverter, first and second capacitors, a resistor, and a transistor. The inverter has an input and an output. The first capacitor is coupled to a ground. The transistor has a first transistor terminal, a second transistor terminal, and a control input. The first transistor terminal is coupled to the first capacitor and the second transistor terminal is coupled to the input of the inverter. The second capacitor is coupled between the output of the inverter and the ground. The resistor is coupled between the output of the inverter and the first transistor terminal.

8. 发明申请

US20200321779A1 Integrated ESD Event Sense Detector 审中-公开
公开(公告)号：US20200321779A1
公开(公告)日：2020-10-08
申请号：US16910656
申请日：2020-06-24
申请人： Texas Instruments Incorporated
发明人： Alan Erik Segervall , Ross Anthony Pimentel , Sumantra Seth
IPC分类号： H02H9/04 , H01L27/02 , H02H1/00
摘要： As an example, a circuit is provided. The circuit includes an ESD (electrostatic discharge) clamping circuit with a control signal controlling clamping operations of the ESD clamping circuit. The circuit further includes a counter coupled to the control signal of the ESD clamping circuit. The counter produces a set of output signals responsive to the control signal. The circuit also includes a communications interface for coupling to the set of output signals of the counter. The communications interface also couples to communications circuitry external to the circuit.

9. 发明申请

US20190173429A1 LOW VOLTAGE FEEDFORWARD CURRENT ASSIST ETHERNET LINE DRIVER 审中-公开
公开(公告)号：US20190173429A1
公开(公告)日：2019-06-06
申请号：US16225043
申请日：2018-12-19
申请人： Texas Instruments Incorporated
发明人： Sumantra Seth , Ashwin Ramachandran , Gururaj Ghorpade
IPC分类号： H03F1/02 , H03F3/45 , H03F3/30 , H03F3/72
摘要： Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.

10. 发明授权

US09065430B2 Architecture for VBUS pulsing in UDSM processes 有权
标题翻译：在UDSM过程中VBUS脉冲的架构
公开(公告)号：US09065430B2
公开(公告)日：2015-06-23
申请号：US14258771
申请日：2014-04-22
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Sumantra Seth , Somasunder Kattepura Sreenath , Sujoy Chinmoy Chakravarty , Arakali Abhijith
IPC分类号： H03K19/094 , G06F13/20 , H03K3/012 , G06F1/26 , H03K19/0185 , H02J7/00
CPC分类号： H03K3/012 , G06F1/26 , H02J2007/0062 , H03K19/0185
摘要： Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.
摘要翻译：用于确保USB-OTG（On Go Go）会话请求协议的Ultra Deep Sub Micron（UDSM）过程中的VBUS脉冲的架构，该体系结构是至少部署充电电路的类型，其使用连接在充电电路的前进路径。该架构可以包括二极管分压器，其包括节点并且在所述充电电路中从VBUS连接。一个实施例使用包括晶体管的充电和放电电路。充电电路晶体管可以包括PMOS晶体管，并且放电电路晶体管可以包括NMOS晶体管。该结构可以包括连接在所述VBUS和地之间的接近100K欧姆的总电阻值的三个电阻串，其中放电电路晶体管可以包括漏极延伸的NMOS晶体管。充电和放电电路晶体管具有约3.6V的VDS和VGD，由此不需要高VGS晶体管。

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