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1. 发明授权

US10854708B2 Capacitor having multiple graphene structures 有权
公开(公告)号：US10854708B2
公开(公告)日：2020-12-01
申请号：US16682381
申请日：2019-11-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chewn-Pu Jou , Chih-Hsin Ko , Po-Wen Chiu , Chao-Ching Cheng , Chun-Chieh Lu , Chi-Feng Huang , Huan-Neng Chen , Fu-Lung Hsueh , Clement Hsingjen Wann
IPC分类号： H01L49/02 , H01L23/528 , H01G4/008 , H01G4/005 , H01L23/522 , H01L23/532 , H01L21/768
摘要： A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.

2. 发明授权

US10673437B2 Level shifting circuit and method 审中-公开
公开(公告)号：US10673437B2
公开(公告)日：2020-06-02
申请号：US16241766
申请日：2019-01-07
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chan-Hong Chern , Tsung-Ching Huang , Chih-Chang Lin , Ming-Chieh Huang , Fu-Lung Hsueh
IPC分类号： H03K5/13 , H03K17/687 , H03K19/0185 , H03K5/00
摘要： A level-shifting circuit includes an input device configured to receive an input signal capable of switching between a reference voltage level and a first voltage level, and a set of capacitive devices paired in series with latch circuits. A first capacitive device of the set is coupled with an output of the input device, and each capacitive device and latch circuit pair is configured to upshift a corresponding received signal by an amount equal to a difference between the first voltage level and the reference voltage level.

3. 发明授权

US10177764B2 Input/output circuit 有权
公开(公告)号：US10177764B2
公开(公告)日：2019-01-08
申请号：US15404812
申请日：2017-01-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chan-Hong Chern , Tsung-Ching Huang , Chih-Chang Lin , Ming-Chieh Huang , Fu-Lung Hsueh
IPC分类号： H03K5/13 , H03K19/0185 , H03K17/687 , H03K5/00
摘要： A circuit includes an output node, a set of first transistors, a set of second transistors, and a first and second power node. The first power node is configured to carry a first voltage level, and second power node is configured to carry a second voltage level. Set of first transistors is coupled between the first power node and output node. Set of second transistors is coupled between the second power node and output node. The first control signal generating circuit is coupled to a gate of a first transistor of the set of first transistors and a gate of a first transistor of the set of second transistors. The first control signal generating circuit is configured to generate a set of biasing signals for the gate of the first transistor of the set of first transistors and the gate of the first transistor of the set of second transistors.

4. 发明授权

US09800154B2 Voltage supply unit and method for operating the same 有权
公开(公告)号：US09800154B2
公开(公告)日：2017-10-24
申请号：US15147383
申请日：2016-05-05
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chan-Hong Chern , Tsung-Ching Huang , Chih-Chang Lin , Ming-Chieh Huang , Fu-Lung Hsueh
IPC分类号： G05F1/575 , H02M3/158 , G05F3/26 , H02M1/08
CPC分类号： H02M3/158 , G05F1/575 , G05F3/262 , H02M1/08
摘要： A voltage supply unit includes a regulator unit, a current mirror, and a cascode unit. The regulator unit is configured to receive first and second voltage signals and generate a third voltage signal. The current mirror is configured to generate first and second current signals based on the third voltage signal. The cascode unit includes a first terminal configured to receive the first current signal, a second terminal configured to receive a first bias voltage signal, a third terminal configured to receive a second bias voltage signal, and a fourth terminal electrically connected to the regulator unit. An output voltage supply signal is controlled by the second current signal.

5. 发明授权

US09531350B2 Level shifters for IO interfaces 有权
标题翻译： IO接口电平移位器
公开(公告)号：US09531350B2
公开(公告)日：2016-12-27
申请号：US13859413
申请日：2013-04-09
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Chih-Chang Lin , Yuwen Swei , Ming-Chieh Huang
IPC分类号： H03K19/0185 , H03K3/02
CPC分类号： H03K3/02 , H03K19/018521 , H03K19/018528
摘要： An integrated circuit which includes a pre-driver configured to receive a first high supply voltage and to generate an input signal and at least one post-driver configured to receive at least one second high supply voltage and to receive the input signal. The at least one post-driver includes an input node configured to receive the input signal and an output node configured to output an output signal. The at least one post-driver further includes a pull-up transistor configured to be in a conductive state during an entire period of operation, and a pull-down transistor. The at least one post-driver further includes at least one diode-connected device coupled between the pull-down transistor and the output node. Each post-driver of the at least one post-driver is configured to supply the output signal having a second voltage level corresponding to a high logic level which is higher than an input voltage level.
摘要翻译：一种集成电路，包括配置成接收第一高电源电压并产生输入信号的预驱动器，以及配置成接收至少一个第二高电源电压并接收输入信号的至少一个后置驱动器。所述至少一个后置驱动器包括被配置为接收输入信号的输入节点和被配置为输出输出信号的输出节点。所述至少一个后置驱动器还包括被配置为在整个操作周期期间处于导通状态的上拉晶体管和下拉晶体管。所述至少一个后驱动器还包括耦合在所述下拉晶体管和所述输出节点之间的至少一个二极管连接器件。所述至少一个后驱动器的每个后驱动器被配置为提供具有对应于高于输入电压电平的高逻辑电平的第二电压电平的输出信号。

6. 发明授权

US09419617B2 Circuit for reducing negative bias temperature instability 有权
标题翻译：降低负偏压温度不稳定性的电路
公开(公告)号：US09419617B2
公开(公告)日：2016-08-16
申请号：US14331711
申请日：2014-07-15
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Ming-Chieh Huang , Bryan Sheffield , Chih-Chang Lin
IPC分类号： H03K19/0175 , H03K19/0185 , H03K19/096 , H03K3/012 , H03K3/3562 , H03K3/356 , H03K19/00
CPC分类号： H03K19/01855 , H03K3/012 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H03K19/0963
摘要： A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to control the output node during a standby mode. The circuit also comprises a transistor coupled to the output node. The control circuit is configured to turn off the transistor during the standby mode.
摘要翻译：电路包括具有输出节点的控制电路。电路还包括耦合到控制电路的半锁存器保持器电路。半锁存器电路被配置为在待机模式期间控制输出节点。电路还包括耦合到输出节点的晶体管。控制电路被配置为在待机模式期间关断晶体管。

7. 发明申请

US20160187380A1 Method and Apparatus for RFID Tag Testing 审中-公开
标题翻译： RFID标签测试方法与设备
公开(公告)号：US20160187380A1
公开(公告)日：2016-06-30
申请号：US15065530
申请日：2016-03-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Hsiung Lee , Kuang-Kai Yen , Yi-Hsuan Liu , Hsieh-Hung Hsieh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： G01R1/067 , G01R31/28 , G01R31/26
CPC分类号： G01R1/06711 , G01R31/2607 , G01R31/28 , G01R31/3025 , G01R31/318511
摘要： A semiconductor wafer includes a plurality of dies and at least one test probe. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit. The at least one test probe includes a plurality of probe pads. The plurality of probe pads is configured to transmit power signals and data to each of the plurality of dies, and to receive test results from each of the plurality of dies. The data are transmitted to each of the plurality of dies in a serial manner. The test results of each of the plurality of dies are also transmitted to the plurality of probe pads in a serial manner.
摘要翻译：半导体晶片包括多个管芯和至少一个测试探针。多个管芯中的每一个都包括射频识别（RFID）标签电路。所述至少一个测试探针包括多个探针垫。多个探针焊盘被配置为将功率信号和数据传送到多个管芯中的每一个，并且从多个管芯中的每一个接收测试结果。以串行方式将数据发送到多个管芯中的每一个。多个管芯中的每一个的测试结果也以串行方式传输到多个探针焊盘。

8. 发明授权

US09360876B2 Voltage supply circuit having an absorption unit and method for operating the same 有权
标题翻译：具有吸收单元的电压供应电路及其操作方法
公开(公告)号：US09360876B2
公开(公告)日：2016-06-07
申请号：US14214362
申请日：2014-03-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chan-Hong Chern , Tsung-Ching Huang , Chih-Chang Lin , Ming-Chieh Huang , Fu-Lung Hsueh
IPC分类号： G05F1/575 , G05F3/26
CPC分类号： H02M3/158 , G05F1/575 , G05F3/262 , H02M1/08
摘要： A voltage supply unit including a regulator unit, a voltage divider and a first current mirror. The regulator unit is configured to receive a first voltage signal and a second voltage signal, and is configured to generate a third voltage signal. The voltage divider is connected between the first current mirror and the regulator unit, and controls the second voltage signal. The first current mirror is connected to the regulator unit, an input voltage supply and the voltage divider. The first current mirror is configured to generate a first current signal and a second current signal, the second current signal is mirrored from the first current signal, the first current signal is controlled by the third voltage signal and the second current signal controls an output voltage supply signal.
摘要翻译：电压供应单元，包括调节器单元，分压器和第一电流镜。调节器单元被配置为接收第一电压信号和第二电压信号，并且被配置为产生第三电压信号。分压器连接在第一电流镜和调节器单元之间，并控制第二电压信号。第一个电流镜连接到调节器单元，一个输入电压源和分压器。第一电流镜被配置为产生第一电流信号和第二电流信号，第二电流信号从第一电流信号镜像，第一电流信号由第三电压信号控制，第二电流信号控制输出电压供电信号。

9. 发明授权

US09255963B2 Built-in self-test circuit for voltage controlled oscillator 有权
标题翻译：用于压控振荡器的内置自测电路
公开(公告)号：US09255963B2
公开(公告)日：2016-02-09
申请号：US14252886
申请日：2014-04-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H03B5/12 , G01R31/28 , H03L5/00
CPC分类号： G01R31/2824 , H03L5/00
摘要： A device comprises a radio frequency peak detector configured to receive an ac signal from a voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector and a feedback control unit coupled between an output of the radio frequency peak detector and an input of the voltage controlled oscillator.
摘要翻译：一种设备包括：射频峰值检测器，被配置为从压控振荡器接收交流信号，并在射频峰值检测器的输出处产生与ac信号成比例的直流值，以及反馈控制单元，其耦合在无线电频率峰值检测器和压控振荡器的输入。

10. 发明授权

US09214933B2 Input/output circuit 有权
标题翻译：输入/输出电路
公开(公告)号：US09214933B2
公开(公告)日：2015-12-15
申请号：US14189653
申请日：2014-02-25
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chan-Hong Chern , Tsung-Ching Huang , Chih-Chang Lin , Ming-Chieh Huang , Fu-Lung Hsueh
IPC分类号： H03K5/13 , H03K17/687 , H03K19/0185 , H03K5/00
CPC分类号： H03K19/018507 , H03K5/13 , H03K17/687 , H03K19/018521 , H03K2005/00013 , H03K2005/00019
摘要： A circuit includes a first power node configured to carry a voltage K·VDD, a second power node configured to carry a zero reference level, an output node, K P-type transistors serially coupled between the first power node and the output node, and K N-type transistors serially coupled between the second power node and the output node. Gates of the K P-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of source-gate voltages or absolute values of drain-gate voltages are equal to or less than VDD. Gates of the K N-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of gate-source voltages or gate-drain voltages are equal to or less than VDD.
摘要翻译：电路包括配置为承载电压K·VDD的第一功率节点，被配置为承载零参考电平的第二功率节点，串联耦合在第一功率节点和输出节点之间的输出节点K P型晶体管，以及 K N型晶体管串联耦合在第二功率节点和输出节点之间。 K P型晶体管的栅极被配置为以一个或多个源极栅极电压的绝对值或漏极 - 栅极电压的绝对值等于或小于VDD的方式接收以一个或多个电压电平设置的偏置信号。 K N型晶体管的栅极被配置为以栅极 - 源极电压或栅极 - 漏极电压的一个或多个绝对值等于或小于VDD的方式接收以一个或多个电压电平设置的偏置信号。

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