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1. 发明授权

US10359695B2 Method of fabricating an integrated circuit with non-printable dummy features 有权
公开(公告)号：US10359695B2
公开(公告)日：2019-07-23
申请号：US15448367
申请日：2017-03-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jyuh-Fuh Lin , Cheng-Hung Chen , Pei-Yi Liu , Wen-Chuan Wang , Shy-Jay Lin , Burn Jeng Lin
IPC分类号： G03F1/36 , G06F17/50 , H01L27/02 , H01L21/762
摘要： The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.

2. 发明申请

US20160284504A1 Electron-Beam Lithography Process with Multiple Columns 有权
标题翻译：具有多列的电子束光刻工艺
公开(公告)号：US20160284504A1
公开(公告)日：2016-09-29
申请号：US14695617
申请日：2015-04-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wen-Chuan Wang , Shy-Jay Lin
IPC分类号： H01J37/147 , H01J37/317
CPC分类号： H01J37/1474 , H01J37/3026 , H01J37/3174 , H01J37/3177 , H01J2237/063 , H01J2237/31766
摘要： The present disclosure provides methods of electron-beam (e-beam) lithography process. The method includes loading a substrate to an electron-beam (e-beam) system such that a first subset of fields defined on the substrate is arrayed on the substrate along a first direction. The method also includes positioning a plurality of e-beam columns having a first subset of e-beam columns arrayed along the first direction. The e-beam columns of the first subset of e-beam columns are directed to different ones of the first subset of fields. The method also includes performing a first exposing process in a scan mode such that the plurality of e-beam columns scans the substrate along the first direction.
摘要翻译：本公开提供了电子束（电子束）光刻工艺的方法。该方法包括将衬底加载到电子束（电子束）系统，使得限定在衬底上的场的第一子集沿着第一方向排列在衬底上。该方法还包括定位多个电子束列，其具有沿第一方向排列的电子束列的第一子集。电子束列的第一子集的电子束列被引导到第一子集子集中的不同子集。该方法还包括以扫描模式执行第一曝光处理，使得多个电子束列沿第一方向扫描基板。

3. 发明授权

US09229332B2 Systems and methods for high-throughput and small-footprint scanning exposure for lithography 有权
标题翻译：用于光刻的高通量和小尺寸扫描曝光的系统和方法
公开(公告)号：US09229332B2
公开(公告)日：2016-01-05
申请号：US14030490
申请日：2013-09-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Burn Jeng Lin , Shy-Jay Lin , Jaw-Jung Shin , Wen-Chuan Wang
IPC分类号： G03B27/32 , G03B27/44 , G03B27/54 , H02K41/02 , G03F7/20
CPC分类号： G03F7/70275 , G03F7/70008 , G03F7/7015 , G03F7/70208 , G03F7/70358 , G03F7/70716 , G03F7/70725 , H01L21/682
摘要： The present disclosure provides a lithography system comprising a radiation source and an exposure tool including a plurality of exposure columns densely packed in a first direction. Each exposure column includes an exposure area configured to pass the radiation source. The system also includes a wafer carrier configured to secure and move one or more wafers along a second direction that is perpendicular to the first direction, so that the one or more wafers are exposed by the exposure tool to form patterns along the second direction. The one or more wafers are covered with resist layer and aligned in the second direction on the wafer carrier.
摘要翻译：本公开提供了一种包括辐射源和曝光工具的光刻系统，该曝光工具包括在第一方向上密集地包装的多个曝光柱。每个曝光列包括配置成通过辐射源的曝光区域。该系统还包括晶片载体，其被配置为沿着垂直于第一方向的第二方向固定和移动一个或多个晶片，使得一个或多个晶片被曝光工具暴露以形成沿着第二方向的图案。一个或多个晶片被抗蚀剂层覆盖，并且在第二方向上在晶片载体上对准。

4. 发明申请

US20150294056A1 Method of Fabricating an Integrated Circuit with Optimized Pattern Density Uniformity 有权
标题翻译：制造具有优化图案密度均匀性的集成电路的方法
公开(公告)号：US20150294056A1
公开(公告)日：2015-10-15
申请号：US14252464
申请日：2014-04-14
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jyuh-Fuh Lin , Pei-Yi Liu , Cheng-Hung Chen , Wen-Chuan Wang , Shy-Jay Lin , Burn Jeng Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36 , G06F17/5009 , G06F17/5081 , G06F2217/12 , H01L27/0207 , Y02P90/265
摘要： The present disclosure provides an IC method that includes receiving an IC design layout having main features; generating a plurality of space block layers to the IC design layout, each of the space block layers being associated with an isolation distance and a plurality of space blocks; calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout; calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space layers according to the main pattern density and the dummy pattern density; choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR; generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio; and forming a tape-out data of the modified IC design layout for IC fabrication.
摘要翻译：本公开提供一种IC方法，包括接收具有主要特征的IC设计布局; 向所述IC设计布局生成多个空间块层，每个所述空间块层与隔离距离和多个空间块相关联; 计算IC设计布局的主图案密度PD0和虚设图案密度PD; 根据主图案密度和虚拟图案密度计算每个空间层的IC设计布局的最小变化块虚拟密度比（LVBDDR）; 根据LVBDDR选择优化的空间块层和优化的块虚拟密度比; 根据优化的空间块层和优化的块虚拟密度比，从IC设计布局生成修改的IC设计布局; 并形成用于IC制造的改进的IC设计布局的输出数据。

5. 发明申请

US20150077731A1 SYSTEMS AND METHODS FOR HIGH-THROUGHPUT AND SMALL-FOOTPRINT SCANNING EXPOSURE FOR LITHOGRAPHY 有权
标题翻译：用于高速切割和小型扫描曝光的系统和方法
公开(公告)号：US20150077731A1
公开(公告)日：2015-03-19
申请号：US14030490
申请日：2013-09-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Burn Jeng Lin , Shy-Jay Lin , Jaw-Jung Shin , Wen-Chuan Wang
IPC分类号： G03F7/20
CPC分类号： G03F7/70275 , G03F7/70008 , G03F7/7015 , G03F7/70208 , G03F7/70358 , G03F7/70716 , G03F7/70725 , H01L21/682
摘要： The present disclosure provides a lithography system comprising a radiation source and an exposure tool including a plurality of exposure columns densely packed in a first direction. Each exposure column includes an exposure area configured to pass the radiation source. The system also includes a wafer carrier configured to secure and move one or more wafers along a second direction that is perpendicular to the first direction, so that the one or more wafers are exposed by the exposure tool to form patterns along the second direction. The one or more wafers are covered with resist layer and aligned in the second direction on the wafer carrier.
摘要翻译：本公开提供了一种包括辐射源和曝光工具的光刻系统，该曝光工具包括在第一方向上密集地包装的多个曝光柱。每个曝光列包括配置成通过辐射源的曝光区域。该系统还包括晶片载体，其被配置为沿着垂直于第一方向的第二方向固定和移动一个或多个晶片，使得一个或多个晶片被曝光工具暴露以形成沿着第二方向的图案。一个或多个晶片被抗蚀剂层覆盖，并且在第二方向上在晶片载体上对准。

6. 发明申请

US20150040079A1 Method for Electron Beam Proximity Correction with Improved Critical Dimension Accuracy 有权
标题翻译：具有改进临界尺寸精度的电子束接近校正方法
公开(公告)号：US20150040079A1
公开(公告)日：2015-02-05
申请号：US13954635
申请日：2013-07-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Cheng-Hung Chen , Jaw-Jung Shin , Shy-Jay Lin , Wen-Chuan Wang , Pei-Yi Liu , Burn Jeng Lin
IPC分类号： G06F17/50
CPC分类号： G03F1/78 , H01J37/3026 , H01J2237/31764 , H01J2237/31771
摘要： The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a feature; fracturing the feature into a plurality of polygons that includes a first polygon; assigning target points to edges of the first polygon; calculating corrected exposure doses to the first polygon, wherein each of the correct exposure doses is determined based on a respective one of the target points by simulation; determining a polygon exposure dose to the first polygon based on the corrected exposure doses; and preparing a tape-out data for lithography patterning, wherein the tape-out data defines the plurality of polygons and a plurality of polygon exposure doses paired with the plurality of polygons.
摘要翻译：本公开提供了集成电路（IC）方法的一个实施例。该方法包括接收具有特征的IC设计布局; 将特征压裂成包括第一多边形的多个多边形; 将目标点分配给第一多边形的边缘; 计算第一多边形的校正曝光剂量，其中通过模拟基于目标点中的相应一个确定每个正确的曝光剂量; 基于所述校正的曝光剂量确定所述第一多边形的多边形曝光剂量; 以及准备用于光刻图案化的输出数据，其中所述输出数据定义所述多个多边形以及与所述多个多边形配对的多个多边形曝光剂量。

7. 发明授权

US08828632B2 Multiple-grid exposure method 有权
标题翻译：多栅曝光法
公开(公告)号：US08828632B2
公开(公告)日：2014-09-09
申请号：US14017749
申请日：2013-09-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wen-Chuan Wang , Shy-Jay Lin , Pei-Yi Liu , Jaw-Jung Shin , Burn Jeng Lin
IPC分类号： G03F9/00 , G03F7/20
CPC分类号： G03F7/2022 , B82Y10/00 , B82Y40/00 , G03F7/20 , G03F7/704 , H01J37/3026 , H01J37/3174 , Y10S430/143
摘要： A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (Δt) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.
摘要翻译：公开了一种制造半导体器件的方法。一种示例性方法包括接收包括网格上的目标图案的集成电路（IC）布局设计。该方法还包括接收多网格结构。多栅格结构包括多个曝光网格段，其在第一方向上彼此偏移一个偏移量。该方法还包括执行多栅格曝光以将衬底上的目标图案曝光，从而在衬底上形成电路特征图案。执行多栅格曝光包括在第二方向上以多栅格结构扫描衬底，使得暴露的目标图案的子像素偏移在第一方向上发生，并且使用增量时间（＆Dgr; t）使得在第二方向上发生曝光的目标图案的子像素偏移。

8. 发明授权

US08822106B2 Grid refinement method 有权
标题翻译：网格细化方法
公开(公告)号：US08822106B2
公开(公告)日：2014-09-02
申请号：US13722266
申请日：2012-12-20
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wen-Chuan Wang , Shy-Jay Lin , Pei-Yi Liu , Jaw-Jung Shin , Burn Jeng Lin
IPC分类号： G03F1/20 , G03F7/20
CPC分类号： G03F7/70058 , G03F7/20 , G03F7/2051 , G03F7/2059 , G03F7/70291 , G03F7/70625 , G06F17/5068 , G06F17/5072 , G06F17/5081
摘要： The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n
摘要翻译：本公开提供了一种用于将临界尺寸（CD）减小因子n（其中n <1）的光刻工艺的方法的实施例。该方法包括提供具有第一像素尺寸S1的图形生成器，以产生具有第二像素尺寸S2的交替数据网格，该第二像素尺寸为

9. 发明申请

US20140217305A1 SYSTEMS AND METHODS PROVIDING ELECTRON BEAM WRITING TO A MEDIUM 有权
标题翻译：提供电子束写入介质的系统和方法
公开(公告)号：US20140217305A1
公开(公告)日：2014-08-07
申请号：US14088155
申请日：2013-11-22
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wen-Chuan Wang , Shy-Jay Lin , Jaw-Jung Shin , Burn Jeng Lin
IPC分类号： G03F7/20
CPC分类号： G03F7/2059 , B82Y10/00 , B82Y40/00 , H01J37/3007 , H01J37/317 , H01J37/3177 , H01J2237/31761 , H01J2237/31774
摘要： A method for electron-beam writing to a medium includes positioning the medium within an e-beam writing machine so that the medium is supported by a stage and is exposed to an e-beam source. The method also includes writing a pattern to the medium using a plurality of independently-controllable beams of the e-beam source, in which the pattern comprises a plurality of parallel strips. Each of the parallel strips is written using multiple ones of the independently-controllable beams.
摘要翻译：用于电子束写入介质的方法包括将介质定位在电子束写入机内，使得介质由载物台支撑并暴露于电子束源。该方法还包括使用电子束源的多个可独立控制的光束将介质写入介质，其中图案包括多个平行条带。使用多个可独立控制的光束来写入每个平行条带。

10. 发明申请

US20130273474A1 Grid Refinement Method 有权
标题翻译：网格细化方法
公开(公告)号：US20130273474A1
公开(公告)日：2013-10-17
申请号：US13722266
申请日：2012-12-20
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Wen-Chuan Wang , Shy-Jay Lin , Pei-Yi Liu , Jaw-Jung Shin , Burn Jeng Lin
IPC分类号： G03F7/20
CPC分类号： G03F7/70058 , G03F7/20 , G03F7/2051 , G03F7/2059 , G03F7/70291 , G03F7/70625 , G06F17/5068 , G06F17/5072 , G06F17/5081
摘要： The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n
摘要翻译：本公开提供了一种用于将临界尺寸（CD）减小因子n（其中n <1）的光刻工艺的方法的实施例。该方法包括提供具有第一像素尺寸S1的图形生成器，以产生具有第二像素尺寸S2的交替数据网格，该第二像素尺寸为

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