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1. 发明申请

US20090217121A1 Decoding Apparatus and Decoding Method 有权
标题翻译：解码装置和解码方法
公开(公告)号：US20090217121A1
公开(公告)日：2009-08-27
申请号：US11912481
申请日：2006-04-20
申请人： Takashi Yokokawa , Toshiyuki Miyauchi , Osamu Shinya
发明人： Takashi Yokokawa , Toshiyuki Miyauchi , Osamu Shinya
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1137 , H03M13/116 , H03M13/6505 , H03M13/6566
摘要： The present invention relates to a decoding apparatus and a decoding method, which are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section 1102 carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results D1101 supplied from a decoding intermediate result storage memory 1104 by way of a cyclic shift circuit 1101, and stores the result of the first computation process in a decoding intermediate result storage memory 1103. A computation section 415 carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results D414 supplied from a decoding intermediate result storage memory 1103 by way of a cyclic shift circuit, and stores the decoding intermediate result D415 in the decoding intermediate result storage memory 1104. The present invention can be applied to, for example, a tuner for receiving (digital) satellite broadcasts.
摘要翻译：解码装置和解码方法技术领域本发明涉及一种能够在防止解码装置的电路规模增大的同时高精度地解码LDPC码的解码装置和解码方法。计算部分1102通过利用通过循环移位电路1101从解码中间结果存储存储器1104提供的解码中间结果D1101来执行与三个校验节点处理相对应的第一计算处理，并且存储第一在解码中间结果存储存储器1103中的计算处理。计算部415通过利用从解码中间结果存储存储器1103提供的解码中间结果D414通过循环的方式执行与六个可变节点处理相对应的第二计算处理并将解码中间结果D415存储在解码中间结果存储存储器1104中。本发明可以应用于例如用于接收（数字）卫星广播的调谐器。

2. 发明授权

US08166363B2 Decoding device and method 失效
标题翻译：解码设备和方法
公开(公告)号：US08166363B2
公开(公告)日：2012-04-24
申请号：US12066641
申请日：2006-09-07
申请人： Osamu Shinya , Takashi Yokokawa , Yuji Shinohara , Toshiyuki Miyauchi
发明人： Osamu Shinya , Takashi Yokokawa , Yuji Shinohara , Toshiyuki Miyauchi
IPC分类号： H03M13/00
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/118 , H03M13/6577 , H04L1/0057
摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
摘要翻译：一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。校验节点计算器（181）执行包括非线性函数的计算的校验节点计算（x）及其非线性函数的反函数＆phgr（-1），以解码LDPC码。可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。校验节点计算器（181）具有LUT，其接收表示具有固定量化宽度的数值的定点量化值，并将非线性函数＆amp;（x）的计算结果作为半浮点数量化值，其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数的计算结果＆phgr; -1（ x）作为固定点量化值。本发明可以应用于例如用于接收卫星广播的调谐器。

3. 发明申请

US20090304111A1 Decoding Device and Method 失效
标题翻译：解码设备和方法
公开(公告)号：US20090304111A1
公开(公告)日：2009-12-10
申请号：US12066641
申请日：2006-09-07
申请人： Osamu Shinya , Takashi Yokokawa , Yuji Shinohara , Toshiyuki Miyauchi
发明人： Osamu Shinya , Takashi Yokokawa , Yuji Shinohara , Toshiyuki Miyauchi
IPC分类号： H03K9/00
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/118 , H03M13/6577 , H04L1/0057
摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
摘要翻译：一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。校验节点计算器（181）执行包括非线性函数phi（x）及其反函数phi-1（x）的计算的校验节点计算，以解码LDPC码。可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。校验节点计算器（181）具有LUT，其接收具有固定量化宽度的表示数值的定点量化值，并将非线性函数phi（x）的计算结果输出为半浮点量化值其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数phi-1（x）的计算结果，作为固定点量化值。本发明可以应用于例如用于接收卫星广播的调谐器。

4. 发明授权

US08086934B2 Decoding apparatus and decoding method 有权
标题翻译：解码装置和解码方法
公开(公告)号：US08086934B2
公开(公告)日：2011-12-27
申请号：US11912481
申请日：2006-04-20
申请人： Takashi Yokokawa , Toshiyuki Miyauchi , Osamu Shinya
发明人： Takashi Yokokawa , Toshiyuki Miyauchi , Osamu Shinya
IPC分类号： H03M13/00
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1137 , H03M13/116 , H03M13/6505 , H03M13/6566
摘要： A decoding apparatus and method are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the result of the first computation process in a decoding intermediate result storage memory. A computation section carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the decoding intermediate result in the decoding intermediate result storage memory.
摘要翻译：解码装置和方法能够以高精度解码LDPC码，同时防止解码装置的电路规模增加。计算部通过循环移位电路利用从解码中间结果存储存储器提供的解码中间结果，对与三个校验节点处理相对应的第一计算处理进行处理，并将第一计算处理的结果存储在解码中间结果存储存储器。计算部通过循环移位电路利用从解码中间结果存储存储器提供的解码中间结果，对与六个可变节点处理相对应的第二计算处理进行解码，并将解码中间结果存储在解码中间结果存储内存

5. 发明授权

US08640010B2 Decoding apparatus and decoding method 失效
标题翻译：解码装置和解码方法
公开(公告)号：US08640010B2
公开(公告)日：2014-01-28
申请号：US12335802
申请日：2008-12-16
申请人： Toshiyuki Miyauchi , Masayuki Hattori , Takashi Yokokawa
发明人： Toshiyuki Miyauchi , Masayuki Hattori , Takashi Yokokawa
IPC分类号： G06F11/00
CPC分类号： H03M13/15 , H03M13/1515 , H03M13/45
摘要： Disclosed herein is a decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus including a hard-decision decoder configured to perform hard-decision decoding on a received word using a hard-decision decoding algorithm; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding merely on a received word for which the hard-decision decoder has failed in the hard-decision decoding.
摘要翻译：本发明公开了一种对线性块码执行软判决解码的解码装置，该装置包括：硬判决解码器，被配置为使用硬判决解码算法对接收到的字执行硬判决解码; 以及软判决解码器，其被配置为仅在硬判决解码器在硬判决解码中已经失败的接收到的字上执行软判决算法的软判决解码。

6. 发明授权

US08451966B2 Information processor and information processing method, display device, and program 有权
标题翻译：信息处理器和信息处理方法，显示设备和程序
公开(公告)号：US08451966B2
公开(公告)日：2013-05-28
申请号：US12567837
申请日：2009-09-28
申请人： Hidetoshi Kawauchi , Toshiyuki Miyauchi , Takashi Yokokawa , Takuya Okamoto , Hiroyuki Kamata
发明人： Hidetoshi Kawauchi , Toshiyuki Miyauchi , Takashi Yokokawa , Takuya Okamoto , Hiroyuki Kamata
IPC分类号： H03D1/06 , H03K5/01 , H03K5/159
CPC分类号： H04L25/0212 , H04L25/022 , H04L25/0232 , H04L27/2647 , H04L27/2665
摘要： Disclosed herein is an information processor, including: a receiving section configured to receive an OFDM signal transmitted in accordance with an OFDM system; a FFT arithmetically operating section configured to carry out FFT for a signal within a predetermined interval of the OFDM signal; a delay profile estimating section configured to estimate delay profiles from the OFDM signal received by the receiving section; an inter-symbol interference amount estimating section configured to estimate inter-symbol interference amounts for a plurality of candidates for the predetermined interval, respectively, by using the delay profiles estimated by the delay profile estimating section; and a searching section configured to search for the candidate having the minimum inter-symbol interference amount estimated by the inter-symbol interference amount estimating section from among the plurality of candidates in the predetermined interval, and supply data on the candidate thus searched for as the predetermined interval to the FFT arithmetically operating section.
摘要翻译：本文公开了一种信息处理器，包括：接收部分，被配置为接收根据OFDM系统传输的OFDM信号; FFT算术运算部，被配置为对所述OFDM信号的预定间隔内的信号进行FFT; 延迟分布估计部，被配置为从所述接收部接收到的OFDM信号估计延迟分布; 符号间干扰量估计部，被配置为通过使用由所述延迟分布估计部估计出的延迟分布，分别估计所述预定间隔的多个候选的符号间干扰量; 以及搜索部，被配置为从所述预定间隔中的所述多个候选中搜索具有由所述符号间干扰量估计部估计的最小符号间干扰量的候选，并且将所搜索的候选者的数据提供为到FFT运算部分的预定间隔。

7. 发明授权

US08238459B2 Decoding device and method, receiving device and method, and program 有权
标题翻译：解码设备和方法，接收设备和方法以及程序
公开(公告)号：US08238459B2
公开(公告)日：2012-08-07
申请号：US12361199
申请日：2009-01-28
申请人： Takashi Yokokawa , Yasuhiro Iida , Toshiyuki Miyauchi , Takashi Hagiwara , Takanori Minamino , Naoya Haneda
发明人： Takashi Yokokawa , Yasuhiro Iida , Toshiyuki Miyauchi , Takashi Hagiwara , Takanori Minamino , Naoya Haneda
IPC分类号： H04L23/02
CPC分类号： H04L27/3827 , H04L1/0054 , H04L1/208 , H04L7/042
摘要： A decoding device that decodes demodulated data obtained by demodulating a quadrature modulated signal arising from digital modulation of a carrier and detects synchronization, the decoding device includes, a decoder configured to decode first demodulated data that is the demodulated data obtained by demodulating the quadrature modulated signal and is composed of in-phase axis data and quadrature axis data. The decoding device decodes second demodulated data obtained by interchanging the in-phase axis data and the quadrature axis data of the first demodulated data. A synchronization detector is configured to detect a boundary between predetermined information symbol sequences from first decoded data obtained by decoding the first demodulated data and detect the boundary from second decoded data obtained by decoding the second demodulated data. The synchronization detector selects and outputs one of the first decoded data and the second decoded data based on a result of the detection of the boundary.
摘要翻译：一种解码装置，对通过解调由载波的数字调制产生的正交调制信号而获得的解调数据进行解码，并检测同步，解码装置包括：解码器，被配置为对作为通过解调正交调制信号而获得的解调数据的第一解调数据进行解码并且由同相轴数据和正交轴数据组成。解码装置对通过交换同相轴数据和第一解调数据的正交轴数据而获得的第二解调数据进行解码。同步检测器被配置为从通过解码第一解调数据获得的第一解码数据检测预定信息符号序列之间的边界，并通过解码第二解调数据获得的第二解码数据检测边界。同步检测器基于边界检测的结果选择并输出第一解码数据和第二解码数据中的一个。

8. 发明申请

US20080168333A1 DECODING METHOD AND DECODING APPARATUS AS WELL AS PROGRAM 有权
标题翻译：解码方法和解码设备作为程序
公开(公告)号：US20080168333A1
公开(公告)日：2008-07-10
申请号：US11959551
申请日：2007-12-19
申请人： Makiko YAMAMOTO , Satoshi Okada , Toshiyuki Miyauchi , Takashi Yokokawa
发明人： Makiko YAMAMOTO , Satoshi Okada , Toshiyuki Miyauchi , Takashi Yokokawa
IPC分类号： H03M13/00
CPC分类号： H03M13/114 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2936 , H03M13/2948 , H03M13/3905 , H03M13/4146
摘要： A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.
摘要翻译：一种用于按接收字的可靠性大小的顺序对接收到的字进行分类的解码方法，使用以对等化的奇偶校验矩阵来执行置信传播，以更新可靠性，并且重复地执行用于更新的可更新的排序和置信传播值包括内部重复解码处理步骤，其使用对应于与所接收到的字的具有相对低的可靠性值的符号相对应的列的顺序对角化的奇偶校验矩阵来执行置信传播，以更新可靠性并基于更新后的重新执行置信传播可靠性; 内部重复解码处理步骤在其重复的第二或更晚的循环中，包括奇偶校验矩阵的有限列的奇偶校验矩阵的对角化。

9. 发明申请

US20050010848A1 Encoding device, encoding method, encoding method program, decoding device, decoding method, decoding method program 失效
标题翻译：编码装置，编码方法，编码方法程序，解码装置，解码方法，解码方法程序
公开(公告)号：US20050010848A1
公开(公告)日：2005-01-13
申请号：US10498936
申请日：2003-10-08
申请人： Takashi Yokokawa , Toshiyuki Miyauchi , Yasuhiro Iida , Kohei Yamamoto , Masayuki Hattori
发明人： Takashi Yokokawa , Toshiyuki Miyauchi , Yasuhiro Iida , Kohei Yamamoto , Masayuki Hattori
IPC分类号： G06F11/10 , H03M13/23 , H03M13/25 , H03M13/27 , H03M13/29 , H04L1/00 , H03M13/00
CPC分类号： H04L1/006 , H03M13/25 , H03M13/258 , H03M13/27 , H03M13/29 , H03M13/2972 , H04L1/0055 , H04L1/0065 , H04L1/0071
摘要： The present invention is particularly applied to serial concatenated coding and serial concatenated trellis coded modulation. In second encoding 107, which is inner coding, a sequence that is not encoded or that is encoded so as to produce a finite impulse response and a sequence that is encoded so as to produce an infinite impulse response are output. In interleaving 106 before the second encoding 107, the sequences are permuted so as not to be mixed with each other.
摘要翻译：本发明特别适用于串联编码和串行级联网格编码调制。在作为内部编码的第二编码器107中，输出未被编码或编码以产生有限脉冲响应的序列和被编码以产生无限脉冲响应的序列。在第二编码107之前的交织106中，将这些序列置换为不相互混合。

10. 发明申请

US20100080330A1 RECEIVING APPARATUS, RECEIVING METHOD, AND PROGRAM 有权
标题翻译：接收设备，接收方法和程序
公开(公告)号：US20100080330A1
公开(公告)日：2010-04-01
申请号：US12567856
申请日：2009-09-28
申请人： Hidetoshi KAWAUCHI , Masayuki Hattori , Toshiyuki Miyauchi , Takashi Yokokawa , Kazuhiro Shimizu , Kazuhisa Funamoto
发明人： Hidetoshi KAWAUCHI , Masayuki Hattori , Toshiyuki Miyauchi , Takashi Yokokawa , Kazuhiro Shimizu , Kazuhisa Funamoto
IPC分类号： H04B1/10
CPC分类号： H04L27/2662 , H04L25/0232 , H04L25/03159 , H04L27/2656 , H04L27/2665
摘要： Disclosed herein is a receiving apparatus including: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.
摘要翻译：本发明公开了一种接收装置，包括：第一至第三位置确定部分，被配置为确定FFT间隔的起始位置，其作为由FFT部分进行FFT的信号间隔; 选择部，被配置为选择由所述第一至第三位置确定部确定的所述FFT间隔的那些起始位置之一; FFT部，被配置为通过将由选择部选择出的开始位置作为FFT间隔的开始位置，对OFDM时域信号进行FFT，以生成第一OFDM频域信号。

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