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1. 发明申请

US20170302287A1 PATTERN BASED ESTIMATION OF ERRORS IN ADC 有权
公开(公告)号：US20170302287A1
公开(公告)日：2017-10-19
申请号：US15485552
申请日：2017-04-12
申请人： Texas Instruments Incorporated
发明人： Srinivas Kumar Reddy Naru , Visvesvaraya Pentakota Appala , Shagun Dusad , Neeraj Shrivastava , Viswanathan Nagarajan , Ani Xavier , Rishi Soundararajan , Sai Aditya Nurani , Roswald Francis
IPC分类号： H03M1/06 , H03M1/12
CPC分类号： H03M1/06 , H03M1/1038 , H03M1/109 , H03M1/1205 , H03M1/164 , H03M1/361
摘要： The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

2. 发明申请

US20230138266A1 METHODS AND APPARATUS TO CALIBRATE A DUAL-RESIDUE PIPELINE ANALOG TO DIGITAL CONVERTER 有权
公开(公告)号：US20230138266A1
公开(公告)日：2023-05-04
申请号：US17515041
申请日：2021-10-29
申请人： Texas Instruments Incorporated
发明人： Prasanth K , Srinivas Kumar Reddy Naru , Visvesvaraya Appala Pentakota
IPC分类号： H03M1/10
摘要： An example apparatus includes: an analog input; a resistor circuit including a first reference output and a second reference output; a first amplifier including a first analog input, a first reference input, and a first amplifier output, the first analog input coupled to the analog input, the first reference input coupled to the first reference output; a second amplifier including a second analog input, a second reference input, and a second amplifier output, the second analog input coupled to the analog input, the second reference input coupled to the second reference output; a first comparator including a first comparator input, the first comparator input coupled to the first amplifier output; and a second comparator including a second comparator input, the second comparator input coupled to the second amplifier output; a first multiplexer including a first multiplexer input and a first residue output, the first multiplexer input coupled to the first amplifier output; and a second multiplexer including a second multiplexer input and a second residue output, the second multiplexer input coupled to the second amplifier output.

3. 发明授权

US10541700B2 Gain and memory error estimation in a pipeline analog to digital converter 有权
公开(公告)号：US10541700B2
公开(公告)日：2020-01-21
申请号：US16249225
申请日：2019-01-16
申请人： Texas Instruments Incorporated
发明人： Srinivas Kumar Reddy Naru , Narasimhan Rajagopal , Shagun Dusad , Viswanathan Nagarajan , Visvesvaraya Appala Pentakota
IPC分类号： H03M1/06 , H03M1/04 , H03M1/16
摘要： In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

4. 发明授权

US10530378B1 Sample based gain error estimation for analog to digital converter 有权
公开(公告)号：US10530378B1
公开(公告)日：2020-01-07
申请号：US16249927
申请日：2019-01-17
申请人： Texas Instruments Incorporated
发明人： Srinivas Kumar Reddy Naru , Nagarajan Viswanathan , Visvesvaraya Pentakota
IPC分类号： H03M1/06
摘要： The disclosure provides a circuit. The circuit includes a zone detection block that generates a control signal in response to an input signal. An amplifier generates an amplified signal in response to the input signal and the control signal. An analog to digital converter (ADC) is coupled to the amplifier and samples the amplified signal to generate a digital signal. A digital corrector is coupled to the zone detection block and the ADC, and transforms the digital signal to generate a rectified signal based on the control signal and an error signal. An error estimator is coupled to the zone detection block and receives the rectified signal as a feedback. The error estimator generates the error signal in response to the control signal and the rectified signal.

5. 发明申请

US20220247421A1 LOOKUP TABLE FOR NON-LINEAR SYSTEMS 有权
公开(公告)号：US20220247421A1
公开(公告)日：2022-08-04
申请号：US17588493
申请日：2022-01-31
申请人： Texas Instruments Incorporated
发明人： Visvesvaraya Appala Pentakota , Srinivas Kumar Reddy Naru , Chirag Shetty , Eeshan Miglani , Neeraj Shrivastava , Narasimhan Rajagopal , Shagun Dusad
IPC分类号： H03M1/10
摘要： In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.

6. 发明授权

US11239851B2 Gain correction for multi-bit successive-approximation register 有权
公开(公告)号：US11239851B2
公开(公告)日：2022-02-01
申请号：US16997975
申请日：2020-08-20
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Srinivas Kumar Reddy Naru , Anand Jerry George , Shagun Dusad , Visvesvaraya Appala Pentakota
IPC分类号： H03M1/00 , H03M1/06 , H03M1/12 , H03M1/46 , H03M1/10 , H03M1/18
摘要： A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.

7. 发明授权

US10341082B1 Delay modulated clock division 有权
公开(公告)号：US10341082B1
公开(公告)日：2019-07-02
申请号：US15906000
申请日：2018-02-27
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Jaiganesh Balakrishnan , Shagun Dusad , Visvesvaraya Pentakota , Srinivas Kumar Reddy Naru , Sarma Sundareswara Gunturi , Nagalinga Swamy Basayya Aremallapur
IPC分类号： H04L7/00 , H03K5/14 , H03K5/00 , H04L9/32
摘要： A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

8. 发明授权

US10320405B2 Pattern based estimation of errors in ADC 有权
公开(公告)号：US10320405B2
公开(公告)日：2019-06-11
申请号：US15909378
申请日：2018-03-01
申请人： Texas Instruments Incorporated
发明人： Srinivas Kumar Reddy Naru , Visvesvaraya Pentakota Appala , Shagun Dusad , Neeraj Shrivastava , Viswanathan Nagarajan , Ani Xavier , Rishi Soundararajan , Sai Aditya Nurani , Roswald Francis
IPC分类号： H03M1/00 , H03M1/06 , H03M1/12 , H03M1/10 , H03M1/16 , H03M1/36
摘要： In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

9. 发明授权

US09479186B1 Gain and offset correction in an interpolation ADC 有权
标题翻译：内插ADC中的增益和偏移校正
公开(公告)号：US09479186B1
公开(公告)日：2016-10-25
申请号：US14871373
申请日：2015-09-30
申请人： Texas Instruments Incorporated
发明人： Srinivas Kumar Reddy Naru , Nagarajan Viswanathan , Visvesvaraya Pentakota
IPC分类号： H03M1/12 , H03M1/06 , H03M1/00 , H03M1/36
CPC分类号： H03M1/0609 , H03M1/203 , H03M1/361
摘要： In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a digital output in response to an input signal. The reference ADC receives a plurality of reference voltages from the main ADC. The plurality of reference voltages includes a first reference voltage and a second reference voltage. The reference ADC generates a reference output in response to the input signal, the first reference voltage and the second reference voltage. A subtractor generates an error signal in response to the digital output and the reference output. A logic block generates one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.
摘要翻译：在所描述的示例中，模数转换器（ADC）包括主ADC和参考ADC。主ADC响应于输入信号产生区域信息信号和数字输出。参考ADC从主ADC接收多个参考电压。多个参考电压包括第一参考电压和第二参考电压。参考ADC根据输入信号，第一参考电压和第二参考电压产生参考输出。减法器响应于数字输出和参考输出产生一个误差信号。响应于区域信息信号，误差信号和参考输出，逻辑块产生第一偏移校正信号，第二偏移校正信号和增益失配信号中的一个。

10. 发明授权

US11881867B2 Calibration scheme for filling lookup table in an ADC 有权
公开(公告)号：US11881867B2
公开(公告)日：2024-01-23
申请号：US17467561
申请日：2021-09-07
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Narasimhan Rajagopal , Eeshan Miglani , Chirag Chandrahas Shetty , Neeraj Shrivastava , Shagun Dusad , Srinivas Kumar Reddy Naru , Nithin Gopinath , Charls Babu , Shivam Srivastava , Viswanathan Nagarajan , Jagannathan Venkataraman , Harshit Moondra , Prasanth K , Visvesvaraya Appala Pentakota
IPC分类号： H03M1/10
CPC分类号： H03M1/1019
摘要： In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

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