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1. 发明申请

US20190131994A1 HIGH-SPEED AND LOW-POWER PIPELINED ADC USING DYNAMIC REFERENCE VOLTAGE AND 2-STAGE SAMPLE-AND-HOLD 审中-公开
公开(公告)号：US20190131994A1
公开(公告)日：2019-05-02
申请号：US16168336
申请日：2018-10-23
申请人： Korea University Research and Business Foundation, Sejong Campus
发明人： Hayun Cecillia CHUNG
IPC分类号： H03M1/12 , H03M1/16
CPC分类号： H03M1/124 , H03M1/1205 , H03M1/1235 , H03M1/164 , H03M1/46
摘要： Disclosed is a high-speed and low-power pipelined analog-digital converter (ADC) using a dynamic reference voltage and a 2-stage S/H. The pipelined ADC includes a 2-stage sample-and-hold (S/H) configured to secure a conversion time corresponding to a clock cycle per stage and to apply only a buffer to an input signal path, a reference voltage generator configured to receive the output of the D flip-flop of a previous stage as an input signal and to generate a required reference voltage during a half cycle of a sample frequency, and a comparator configured to include a linear transconductor (LT), a rail-to-rail latch (R2R) and a D flip-flop and to generate the output of the ADC and input to the reference voltage generator of a next stage for generating a reference voltage using the output of the D flip-flop.

2. 发明授权

US09900538B2 Phase delay counting analog-to-digital converter circuitry 有权
公开(公告)号：US09900538B2
公开(公告)日：2018-02-20
申请号：US15157677
申请日：2016-05-18
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Ha Le-Thai , Tomas Geurts , Georges Gielen
IPC分类号： H04N5/378 , H03M1/12
CPC分类号： H04N5/378 , H03M1/1205 , H03M1/123 , H03M1/1245 , H03M1/14 , H03M1/52 , H04N5/3575 , H04N5/374
摘要： An analog-to-digital converter may include an integrator, a gated ring oscillator, a coarse counter, a phase state register, a counter register, and logic circuitry. The gated ring oscillator may output a phase state signal continuously to the phase state register. The phase state signal includes multiple phase nodes, each of which is created by transmitting a signal through a number of delay stages. One of the phase nodes may be provided to the coarse counter. The phase state register and counter register may store the most current corresponding phase state and coarse counter outputs, respectively. A control signal corresponding to an analog image input signal may control the output of stored phase states and stored coarse counter outputs to the logic circuitry. The logic circuitry may generate a digital version of the analog image input signal based on the outputs of the phase state and counter registers.

3. 发明授权

US09843335B2 Supervision of input signal channels 有权
公开(公告)号：US09843335B2
公开(公告)日：2017-12-12
申请号：US15391521
申请日：2016-12-27
申请人： Schweitzer Engineering Laboratories, Inc.
发明人： Edmund O. Schweitzer, III , Veselin Skendzic , Tracey G. Windley , Bogdan Z. Kasztenny
IPC分类号： H03M1/00 , H03M1/06 , H03M1/10 , H03M1/12
CPC分类号： H03M1/0607 , G01R31/086 , H03M1/1023 , H03M1/1076 , H03M1/12 , H03M1/1205
摘要： The present disclosure pertains to systems and methods for monitoring a plurality of analog-to-digital converters. In one embodiment, a plurality of input channels may each be in communication with a different phase of a three-phase electric power delivery system. The input channels may be configured to receive analog signals from the different phases. A composite signal subsystem may be configured to generate a composite signal based on the plurality of input channels. An analog-to-digital converter subsystem may be configured to produce a digitized representation of each of the plurality of input channels and a digitized representation of the composite signal. An analog-to-digital converter monitor subsystem may identify an error in the analog-to-digital conversion based on the digitized representation of the composite signal and the digitized representations of the plurality of input channels.

4. 发明申请

US20170187385A1 Supervision of Input Signal Channels 有权
公开(公告)号：US20170187385A1
公开(公告)日：2017-06-29
申请号：US15391521
申请日：2016-12-27
申请人： Schweitzer Engineering Laboratories, Inc.
发明人： Edmund O. Schweitzer, III , Veselin Skendzic , Tracey G. Windley , Bogdan Z. Kasztenny
IPC分类号： H03M1/06 , H03M1/12 , H03M1/10
CPC分类号： H03M1/0607 , G01R31/086 , H03M1/1023 , H03M1/1076 , H03M1/12 , H03M1/1205
摘要： The present disclosure pertains to systems and methods for monitoring a plurality of analog-to-digital converters. In one embodiment, a plurality of input channels may each be in communication with a different phase of a three-phase electric power delivery system. The input channels may be configured to receive analog signals from the different phases. A composite signal subsystem may be configured to generate a composite signal based on the plurality of input channels. An analog-to-digital converter subsystem may be configured to produce a digitized representation of each of the plurality of input channels and a digitized representation of the composite signal. An analog-to-digital converter monitor subsystem may identify an error in the analog-to-digital conversion based on the digitized representation of the composite signal and the digitized representations of the plurality of input channels.

5. 发明申请

US20170118505A1 METHOD AND APPARATUS FOR AN ENERGY-EFFICIENT RECEIVER 审中-公开
公开(公告)号：US20170118505A1
公开(公告)日：2017-04-27
申请号：US15400666
申请日：2017-01-06
申请人： MaxLinear, Inc.
发明人： Curtis Ling
IPC分类号： H04N21/436 , H04N21/442 , H04N21/462 , H04N21/4143 , H04N21/426
CPC分类号： H04N21/43615 , H03M1/1205 , H04B1/16 , H04H40/90 , H04H60/82 , H04N7/20 , H04N21/4143 , H04N21/42607 , H04N21/44227 , H04N21/462 , H04N21/6143 , Y02D70/00 , Y02D70/168 , Y02D70/21
摘要： One or more circuits may comprise at least one first-type analog-to-digital converter (ADC) and at least one second-type ADC. The circuit(s) may be operable to receive a plurality of signals, each of which may comprise a plurality of channels. The circuit(s) may be operable to digitize a selected one or more of the channels. Which, if any, of the selected channels are digitized via the at least one first-type ADC and which, if any, of the selected channels are digitized via the at least one second-type ADC, may be based on which of the plurality of channels are the selected channels and/or based on power consumption of the circuit(s). A bandwidth of each first-type ADC may be on the order of the bandwidth of one of the received signals. A bandwidth of each second-type ADC may be on the order of the bandwidth of one of the plurality of channels.

6. 发明授权

US09634667B2 Integrated circuit device with programmable analog subsystem 有权
公开(公告)号：US09634667B2
公开(公告)日：2017-04-25
申请号：US14668984
申请日：2015-03-26
申请人： Cypress Semiconductor Corporation
发明人： Eashwar Thiagarajan , Harold M. Kutz , Hans Klein , Jaskarn Singh Johal , Jean-Paul Vanitegem , Kendall V. Castor-Perry , Mark E. Hastings , Amsby D. Richardson, Jr. , Anasuya Pai Maroor , Ata Khan , Dennis R. Seguine , Bruce E. Byrkett , Carl Ferdinand Liepold , Hans Van Antwerpen
IPC分类号： H03K19/177 , H03K19/0175 , H03K19/02 , H03K19/00 , H03K19/003 , H03M1/12 , H03M1/38
CPC分类号： H03K19/017581 , H03K19/0005 , H03K19/00346 , H03K19/02 , H03M1/1205 , H03M1/38
摘要： An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.

7. 发明申请

US20170047935A1 ANALOG-TO-DIGITAL CONVERSION WITH NOISE INJECTION VIA WAVEFRONT MULTIPLEXING TECHNIQUES 审中-公开
标题翻译：通过WAVEFRONT多路复用技术进行噪声注入的模拟数字转换
公开(公告)号：US20170047935A1
公开(公告)日：2017-02-16
申请号：US15339882
申请日：2016-10-31
申请人： SPATIAL DIGITAL SYSTEMS, INC.
发明人： Donald C.D. Chang , Tzer-Hso Lin , Yuanchang Liu
IPC分类号： H03M1/00 , H03M1/12 , H03M1/20 , H03M1/08
CPC分类号： H03M1/002 , H03M1/0641 , H03M1/08 , H03M1/12 , H03M1/1205 , H03M1/1215 , H03M1/188 , H03M1/20 , H04B1/0475 , H04B1/123 , H04B7/10 , H04L27/06
摘要： An analog-to-digital conversion system comprises a first processor, a bank of N analog-to-digital converters, and a second processor. The first processor is configured to receive M input signal streams, perform a wave-front multiplexing transform in analog domain on the M input signal streams and output concurrently N mixed signal streams, M and N being integers and N≧M>1. The wave-front multiplexing transform comprises a first set of wave-front vectors. The bank of N analog-to-digital converters is coupled to the first processor. The N analog-to-digital converters convert the N mixed signal streams from analog format to digital format and output concurrently N digital data streams. The second processor is coupled to the bank of N analog-to-digital converters. The second processor is configured to receive the N digital data streams, perform a wave-front de-multiplexing transform in digital domain on the N digital data streams and output concurrently N output data streams such that the N output data streams comprise M output data streams that correspond respectively to the M input signal streams. The wave-front de-multiplexing transform comprises a second set of wave-front vectors.
摘要翻译：模数转换系统包括第一处理器，一组N个模数转换器和第二处理器。第一处理器被配置为接收M个输入信号流，在M个输入信号流上以模拟域执行波前复用变换，同时输出N个混合信号流，M和N为整数，N≥M> 1。波前复用变换包括第一组波前向量。 N模拟数字转换器的组合耦合到第一处理器。 N个模数转换器将N个混合信号流从模拟格式转换为数字格式，同时输出N个数字数据流。第二处理器耦合到N个模数转换器组。第二处理器被配置为接收N个数字数据流，对N个数字数据流中的数字域执行波前解复用变换并且同时输出N个输出数据流，使得N个输出数据流包括M个输出数据流分别对应于M个输入信号流。波前解复用变换包括第二组波前向量。

8. 发明申请

US20160352350A1 ANALOG/DIGITAL CONVERSION CIRCUIT 有权
标题翻译：模拟/数字转换电路
公开(公告)号：US20160352350A1
公开(公告)日：2016-12-01
申请号：US15117246
申请日：2015-05-18
申请人： DENSO CORPORATION
发明人： Yukihiko TANIZAWA
IPC分类号： H03M1/38 , H03M1/12
CPC分类号： H03M1/38 , H03M1/0619 , H03M1/10 , H03M1/1205 , H03M1/50
摘要： An A/D conversion circuit includes: first/second pulse circulation circuits delaying an input signal and circulating a pulse signal; a circulation number difference measurement section outputting a difference between circulation time numbers of the pulse signal through the first/second pulse circulation circuits; a conversion control circuit outputting the difference as A/D conversion data when outputting a conversion data output processing signal; and a signal ratio change circuit: outputting, from a first output terminal, a voltage calculated by adding the reference voltage and a voltage obtained by multiplying a differential voltage, obtained by subtracting the reference voltage from the analog input voltage, by a first proportional coefficient; and outputting, from a second output terminal, a voltage calculated by subtracting, from the reference voltage, a voltage obtained by multiplying the differential voltage by a second proportional coefficient. The first/second pulse circulation circuits receive power source voltage supply from the first/second output terminals and a ground line.
摘要翻译： A / D转换电路包括：第一/第二脉冲循环电路延迟输入信号并循环脉冲信号; 输出通过第一/第二脉冲循环回路的脉冲信号的循环时间数之间的差的循环次数差测量部; 转换控制电路，当输出转换数据输出处理信号时，将差值作为A / D转换数据输出; 信号比变更电路：从第一输出端子输出通过将基准电压加上的电压和通过将从模拟输入电压减去基准电压而获得的差分电压乘以第一比例系数而获得的电压 ; 并且从第二输出端子输出通过从所述参考电压减去通过将所述差分电压乘以第二比例系数而获得的电压而计算的电压。第一/第二脉冲循环电路从第一/第二输出端子和接地线接收电源电压。

9. 发明授权

US09252799B2 Receiver with orthogonal beam forming technique 有权
标题翻译：接收机采用正交波束成形技术
公开(公告)号：US09252799B2
公开(公告)日：2016-02-02
申请号：US12951995
申请日：2010-11-22
申请人： Donald C. D. Chang , Yulan Sun , Frank Lu
发明人： Donald C. D. Chang , Yulan Sun , Frank Lu
IPC分类号： H04L27/06 , H03M1/20 , H03M1/12 , H03M1/06 , H04B1/04 , H04B7/10 , H03M1/00 , H03M1/08 , H03M1/18
CPC分类号： H03M1/002 , H03M1/0641 , H03M1/08 , H03M1/12 , H03M1/1205 , H03M1/1215 , H03M1/188 , H03M1/20 , H04B1/0475 , H04B1/123 , H04B7/10 , H04L27/06
摘要： A receiver with orthogonal beam forming technique is achieved that is capable of differentiating different signal components within the received composite signal. An adaptive processor is used to eliminate the signal component whose phase information is known or can be calculated. The phase information of the major component of a signal can be easily acquired by using a limiter. The phase information of other signal components can be acquired by their direction information and other characteristics, such as modulation scheme, etc. Multiple orthogonal beams can be formed by eliminating one unwanted signal component each time by the adaptive processor until all unwanted signal is eliminated. Thus, a composite signal from multiple sources can be broken down into their component signals.
摘要翻译：实现了具有正交波束形成技术的接收机，其能够区分接收到的复合信号中的不同信号分量。使用自适应处理器来消除其相位信息已知或可被计算的信号分量。可以通过使用限制器容易地获取信号的主要成分的相位信息。其他信号分量的相位信息可以通过它们的方向信息和诸如调制方案等的其它特性来获取。可以通过自适应处理器每次消除一个不需要的信号分量来形成多个正交波束，直到消除所有不需要的信号。因此，来自多个源的复合信号可以被分解成它们的分量信号。

10. 发明授权

US09178525B2 Mismatch corrector 有权
标题翻译：不匹配校正器
公开(公告)号：US09178525B2
公开(公告)日：2015-11-03
申请号：US14656122
申请日：2015-03-12
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Sthanunathan Ramakrishnan , Sreenath Narayanan Potty
IPC分类号： H03M1/10 , H03M1/12 , H03M1/06
CPC分类号： H03M1/121 , H03M1/06 , H03M1/0626 , H03M1/0639 , H03M1/1205 , H03M1/1215
摘要： A mismatch corrector can include a correction path comprising a plurality of parallel branches that each includes a correction filter that applies a respective one of a plurality of time domain filter coefficients that corresponds to a function of a mismatch profile of an interleaved analog-to-digital (IADC) signal on the IADC signal. The mismatch corrector can also include a delay path that delays the IADC signal by a predetermined number of samples to provide a delayed version of the IADC signal. The mismatch corrector can further include a summer to subtract an output of each correction filter from the delayed version of the IADC signal to generate a corrected IADC signal.
摘要翻译：不匹配校正器可以包括校正路径，其包括多个并行分支，每个分支包括校正滤波器，校正滤波器应用与交织的模数转换器的失配曲线的函数相对应的多个时域滤波器系数中的相应一个（IADC）信号。不匹配校正器还可以包括将IADC信号延迟预定数量的采样以提供IADC信号的延迟版本的延迟路径。不匹配校正器还可以包括加法器，以从IADC信号的延迟版本中减去每个校正滤波器的输出，以产生校正的IADC信号。

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