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1. 发明授权

US06903983B2 Semiconductor integrated circuit device and read start trigger signal generating method therefor 有权
标题翻译：半导体集成电路器件及其读取开始触发信号产生方法
公开(公告)号：US06903983B2
公开(公告)日：2005-06-07
申请号：US10325753
申请日：2002-12-23
申请人： Tokumasa Hara , Hidetoshi Saito , Hitoshi Shiga , Yasuhiko Honda , Tadayuki Taura , Hideo Kato
发明人： Tokumasa Hara , Hidetoshi Saito , Hitoshi Shiga , Yasuhiko Honda , Tadayuki Taura , Hideo Kato
IPC分类号： G11C16/02 , G11C8/18 , G11C16/32 , G11C16/04
CPC分类号： G11C8/18 , G11C16/32 , G11C2216/22
摘要： A semiconductor integrated circuit device includes a first memory cell array corresponding to bank 0, a second memory cell array corresponding to bank 1, first address transition signal generating circuits which detect transitions of input addresses and generate first address transition signals, a second address transition signal generating circuit which pre-detects an end of automatic execution of bank 0 or bank 1 and generates a second address transition signal, and a read start trigger output circuit. The read start trigger output circuit outputs a read start trigger signal on the basis of the first address transition signals and the second address transition signal.
摘要翻译：半导体集成电路装置包括对应于存储体0的第一存储单元阵列，对应于存储体1的第二存储单元阵列，检测输入地址的转换并产生第一地址转换信号的第一地址转换信号产生电路，第二地址转换信号生成电路，其预先检测存储体0或存储体1的自动执行结束并产生第二地址转换信号，以及读取开始触发输出电路。读取开始触发输出电路基于第一地址转换信号和第二地址转换信号输出读取开始触发信号。

2. 发明授权

US06778443B2 Non-volatile semiconductor memory device having memory blocks pre-programmed before erased 失效
标题翻译：具有在擦除前被预先编程的存储器块的非易失性半导体存储器件
公开(公告)号：US06778443B2
公开(公告)日：2004-08-17
申请号：US10328149
申请日：2002-12-23
申请人： Hitoshi Shiga , Tokumasa Hara , Tadayuki Taura
发明人： Hitoshi Shiga , Tokumasa Hara , Tadayuki Taura
IPC分类号： G11C1604
CPC分类号： G11C16/107 , G11C16/16 , G11C16/344 , G11C16/3445
摘要： A non-volatile semiconductor memory device comprises a plurality of blocks each having a plurality of memory cells to be erased at a time and a decoder for selecting the memory cells, each of the blocks having a block decoder for latching a selection signal thereof in pre-programming and for selecting all of the latched blocks by the selection signal at the same time, a sense amplifier, and an address control circuit for controlling a sequence, the sequence including counting addresses of the memory cells in erasing and erasing all of the selected memory cells after pre-programming, all of the blocks having the latched selection signal being controlled to be collectively erased by the address control circuit.
摘要翻译：一种非易失性半导体存储器件包括多个块，每个块具有一次要擦除的多个存储器单元和用于选择存储器单元的解码器，每个块具有块解码器，用于将其选择信号锁存在预先编程并用于同时通过选择信号选择所有锁存块，读出放大器和用于控制序列的地址控制电路，该序列包括擦除和擦除所有所选择的所有存储单元的计数地址预编程后的存储单元，具有锁存选择信号的所有块被控制为由地址控制电路共同擦除。

3. 发明授权

US06928002B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06928002B2
公开(公告)日：2005-08-09
申请号：US10884739
申请日：2004-07-01
申请人： Hitoshi Shiga , Tokumasa Hara , Tadayuki Taura
发明人： Hitoshi Shiga , Tokumasa Hara , Tadayuki Taura
IPC分类号： G11C16/16 , G11C16/34 , G11C16/04
CPC分类号： G11C16/107 , G11C16/16 , G11C16/344 , G11C16/3445
摘要： A non-volatile semiconductor memory device comprises a plurality of blocks each having a plurality of memory cells to be erased at a time and a decoder for selecting the memory cells, each of the blocks having a block decoder for latching a selection signal thereof in pre-programming and for selecting all of the latched blocks by the selection signal at the same time, a sense amplifier, and an address control circuit for controlling a sequence, the sequence including counting addresses of the memory cells in erasing and erasing all of the selected memory cells after pre-programming, all of the blocks having the latched selection signal being controlled to be collectively erased by the address control circuit.
摘要翻译：一种非易失性半导体存储器件包括多个块，每个块具有一次要擦除的多个存储器单元和用于选择存储器单元的解码器，每个块具有块解码器，用于将其选择信号锁存在预先编程并用于同时通过选择信号选择所有锁存块，读出放大器和用于控制序列的地址控制电路，该序列包括擦除和擦除所有所选择的所有存储单元的计数地址预编程后的存储单元，具有锁存选择信号的所有块被控制为由地址控制电路共同擦除。

4. 发明授权

US06795352B2 Nonvolatile semiconductor memory having page mode with a plurality of banks 失效
标题翻译：具有多个存储体的页面模式的非易失性半导体存储器
公开(公告)号：US06795352B2
公开(公告)日：2004-09-21
申请号：US10703005
申请日：2003-11-05
申请人： Toru Tanzawa , Shigeru Atsumi , Akira Umezawa , Tadayuki Taura , Hitoshi Shiga , Yoshinori Takano
发明人： Toru Tanzawa , Shigeru Atsumi , Akira Umezawa , Tadayuki Taura , Hitoshi Shiga , Yoshinori Takano
IPC分类号： G11C1604
CPC分类号： G11C16/0408 , G11C16/08 , G11C16/26 , G11C29/70
摘要： The semiconductor memory comprises a reference current generator, first and second current converters, sense amplifiers for read, and sense amplifiers for verify. The reference current generator generates a first voltage dependent upon the current flowing through a reference cell. The first current converters, to which the first voltage is input, each generate a second voltage. The second current converters, to which the first voltage is input, each generate a third voltage. The sense amplifiers for read output data of a selection memory cell, comparing the voltage of the data-line for read with the second voltage. The sense amplifiers for verify output verify data of the selection memory cell, comparing the voltage of the data-lines for verify and the third voltage.
摘要翻译：半导体存储器包括参考电流发生器，第一和第二电流转换器，用于读出的读出放大器和用于验证的读出放大器。参考电流发生器根据流过参考单元的电流产生第一电压。输入第一电压的第一电流转换器各自产生第二电压。第一电压输入的第二电流转换器各自产生第三电压。读出放大器，用于选择存储器单元的读取输出数据，将用于读取的数据线的电压与第二电压进行比较。用于验证输出的读出放大器验证选择存储单元的数据，比较用于验证的数据线的电压和第三电压。

5. 发明授权

US06888764B2 Semiconductor device including semiconductor memory 失效
标题翻译：包括半导体存储器的半导体器件
公开(公告)号：US06888764B2
公开(公告)日：2005-05-03
申请号：US10231283
申请日：2002-08-30
申请人： Hitoshi Shiga , Tadayuki Taura , Shigeru Atsumi
发明人： Hitoshi Shiga , Tadayuki Taura , Shigeru Atsumi
IPC分类号： G01R31/28 , G11C16/02 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/04 , G11C29/10 , G11C29/12 , G11C7/00
CPC分类号： G11C29/76 , G11C16/04 , G11C2029/1802
摘要： A semiconductor device has an address counter to output, in a first mode, a first block address whereas, in a second mode, a second block address selected from a block-address space two times larger than a block-address space corresponding to memory blocks, the memory blocks and at least one redundant block being included in a memory section, and a block-selection controller, in the second mode, one of the memory blocks, which corresponds to the output of the address counter, when the most significant value of the second block address as the output of the address counter is at a first level whereas select the redundant block while the memory blocks are inhibited from selection, when the most significant value is at a second level.
摘要翻译：半导体器件具有地址计数器，以第一模式输出第一块地址，而在第二模式中，从与存储块对应的块地址空间大2倍的块地址空间中选择第二块地址存储器块和至少一个冗余块被包括在存储器部分中，以及块选择控制器，在第二模式中，当最大有效值时对应于地址计数器的输出的存储块之一作为地址计数器的输出的第二块地址处于第一级，而当最高有效值处于第二级时，选择该冗余块而存储块被禁止选择。

6. 发明授权

US06671203B2 Nonvolatile semiconductor memory having page mode with a plurality of banks 有权
标题翻译：具有多个存储体的页面模式的非易失性半导体存储器
公开(公告)号：US06671203B2
公开(公告)日：2003-12-30
申请号：US10233133
申请日：2002-08-30
申请人： Toru Tanzawa , Shigeru Atsumi , Akira Umezawa , Tadayuki Taura , Hitoshi Shiga , Yoshinori Takano
发明人： Toru Tanzawa , Shigeru Atsumi , Akira Umezawa , Tadayuki Taura , Hitoshi Shiga , Yoshinori Takano
IPC分类号： G11C1604
CPC分类号： G11C16/0408 , G11C16/08 , G11C16/26 , G11C29/70
摘要： A nonvolatile semiconductor memory includes first and second nonvolatile memory banks, a data-line for read, a data-line for program and verify, a sense amplifier for read, a sense amplifier for program and verify, and a program circuit. The data-lines are arranged in a region between the first and second nonvolatile memory banks, and selectively connected to the bit-lines of the first and second nonvolatile memory banks. The sense amplifier for read is connected to the data-line for read. The sense amplifier for program and verify and the program circuit are connected to the data-line for program and verify.
摘要翻译：非易失性半导体存储器包括第一和第二非易失性存储器组，用于读取的数据线，用于编程和验证的数据线，用于读取的读出放大器，用于编程和验证的读出放大器以及程序电路。数据线布置在第一和第二非易失性存储体之间的区域中，并且选择性地连接到第一和第二非易失性存储体的位线。用于读取的读出放大器连接到数据线进行读取。用于程序和验证的读出放大器和程序电路连接到数据线进行程序和验证。

7. 发明授权

US09043679B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09043679B2
公开(公告)日：2015-05-26
申请号：US13719479
申请日：2012-12-19
申请人： Hitoshi Shiga , Hidetaka Tsuji
发明人： Hitoshi Shiga , Hidetaka Tsuji
IPC分类号： G11C29/00 , G06F11/10 , G11C29/04
CPC分类号： G06F11/1008 , G06F11/1072 , G11C2029/0411
摘要： A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation. The external controller includes an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data. The internal controller outputs the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.
摘要翻译：存储器件包括存储数据的存储器芯片和控制存储器芯片的外部控制器。存储器芯片包括被配置为存储两个或多个位的数据的多个存储器单元; 以及内部控制器，其执行包括下页和上页程序操作的页面数据的编程操作，并且对包括下页和上页读操作的页数据执行读操作。外部控制器包括纠错单元，对要编程到存储单元阵列中的数据进行纠错编码，并对数据执行纠错解码。在上层读取操作中，内部控制器将读取页数据从存储单元阵列输出到外部控制器，而不管高层编程操作是否完成。

8. 发明授权

US07978512B2 Semiconductor memory system 有权
标题翻译：半导体存储器系统
公开(公告)号：US07978512B2
公开(公告)日：2011-07-12
申请号：US12557898
申请日：2009-09-11
申请人： Hitoshi Shiga
发明人： Hitoshi Shiga
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G06F11/1072 , G11C11/5628 , G11C16/0483 , G11C29/00 , G11C2211/5641 , H01L27/11521
摘要： A semiconductor memory system includes: a memory cell array having a plurality of memory cells arranged therein, the plurality of memory cells capable of storing N bits of information in each memory cell (where N is a natural number more than 3, other than a power of two); a control circuit configured to control read, write, and erase operations on the memory cell array; and an ECC circuit configured to correct data read from the memory cell array, based on redundant data. The memory cells that share one of word lines and can be written or read at a time are configured to store multiple pages of data therein. A total amount of data stored in the multiple pages is set to a power-of-two number of bits, and the redundant data is stored in a residual portion of the multiple pages.
摘要翻译：半导体存储器系统包括：存储单元阵列，其中布置有多个存储器单元，所述多个存储单元能够在每个存储单元中存储N位信息（其中N是大于3的自然数，除了功率的两个）; 控制电路，被配置为控制对所述存储单元阵列的读，写和擦除操作; 以及ECC电路，被配置为基于冗余数据校正从存储单元阵列读取的数据。共享字线之一并且可以一次写入或读取的存储单元被配置为在其中存储多页数据。存储在多页中的数据的总量被设置为两位数，并且冗余数据被存储在多页的剩余部分中。

9. 发明授权

US07843724B2 Nonvolatile semiconductor memory and data reading method 失效
标题翻译：非易失性半导体存储器和数据读取方法
公开(公告)号：US07843724B2
公开(公告)日：2010-11-30
申请号：US11863915
申请日：2007-09-28
申请人： Hitoshi Shiga , Susumu Fujimura , Yoshihiko Shindo
发明人： Hitoshi Shiga , Susumu Fujimura , Yoshihiko Shindo
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5646
摘要： A nonvolatile semiconductor memory that includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section. The data reading and programming cortrol section includes: an adjacent memory cell data reading section; an adjacent memory cell data memory section; a reading voltage level control section; a data reading section for reading the data from a first memory cell at a plurality of reading voltages corresponding to a plurality of predetermined reading voltage verify levels controlled using the reading voltage level control section; and a data determining section for deterraining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section.
摘要翻译：一种非易失性半导体存储器，包括：包括多个电可写入存储单元的存储单元阵列; 连接到所述多个存储单元的多个字线和多个位线; 和数据读取和编程控制部分。数据读取和编程cortrol部分包括：相邻的存储单元数据读取部分; 相邻存储单元数据存储器部分; 读取电压电平控制部; 数据读取部分，用于以对应于使用读取电压电平控制部分控制的多个预定读取电压验证电平的多个读取电压读取来自第一存储器单元的数据; 以及数据确定部分，用于基于由数据读取部分读取的数据来确定在第一存储器单元中编程4值数据的哪个数据。

10. 发明授权

US07522452B2 Non-volatile semiconductor storage device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07522452B2
公开(公告)日：2009-04-21
申请号：US11769383
申请日：2007-06-27
申请人： Hitoshi Shiga
发明人： Hitoshi Shiga
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C29/88 , G11C2211/5621 , G11C2211/5646
摘要： A memory cell array includes a plurality of memory cells enabled to store multi-value data. A bit-line control circuit includes data storage circuits connected to bit-lines and each store one of a plurality of sets of page data included in the multi-value data, the bit-line control circuit controlling bit-line voltages applied to the bit-lines. A word-line control circuit controls a word-line voltage applied to a word-line. A control circuit controls the word-line control circuit and the bit-line control circuit. The control circuit performs a mode in which, to distinguish a fault block, all or specific memory cells in a fault block may be written so that all or specific memory cells in the fault block have a threshold voltage higher than a word-line voltage applied to a selected word-line when reading a first page data of the sets of page data.
摘要翻译：存储单元阵列包括能够存储多值数据的多个存储单元。位线控制电路包括连接到位线的数据存储电路，并且每个存储包括在多值数据中的多组页数据中的一个，位线控制电路控制施加到位的位线电压线。字线控制电路控制施加到字线的字线电压。控制电路控制字线控制电路和位线控制电路。控制电路执行这样的模式，为了区分故障块，可以写入故障块中的全部或特定存储单元，使得故障块中的全部或特定存储单元的阈值电压高于施加的字线电压当读取页面数据集合的第一页数据时，到所选择的字线。

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