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1. 发明授权

US08154916B2 Nonvolatile memory circuit using spin MOS transistors 有权
标题翻译：使用自旋MOS晶体管的非易失性存储电路
公开(公告)号：US08154916B2
公开(公告)日：2012-04-10
申请号：US12889881
申请日：2010-09-24
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： G11C11/14
CPC分类号： G11C14/0081
摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
摘要翻译：某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

2. 发明申请

US20120074984A1 LOOK-UP TABLE CIRCUITS AND FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：查看表电路和现场可编程门阵列
公开(公告)号：US20120074984A1
公开(公告)日：2012-03-29
申请号：US13238020
申请日：2011-09-21
申请人： Hideyuki SUGIYAMA , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki SUGIYAMA , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： H03K19/177 , H03K5/00
CPC分类号： H03K19/177
摘要： A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.
摘要翻译：根据实施例的查找表电路包括：可变电阻电路，包括可变电阻器件，并且基于输入信号从可变电阻器件中选择可变电阻器件; 参考电路，其具有可变电阻电路的最大电阻值和最小电阻值之间的电阻值; 第一n沟道MOSFET，其包括连接到可变电阻电路的端子的源极和连接到漏极的栅极; 第二n沟道MOSFET，其包括连接到参考电路的端子的源极和连接到第一n沟道MOSFET的栅极的栅极; 用于向可变电阻电路提供电流的第一电流供应电路; 第二电流供应电路，用于向参考电路提供电流; 以及比较器，用于比较第一输入端和第二输入端的电压。

3. 发明授权

US09112139B2 Spin transistor and memory 有权
标题翻译：旋转晶体管和存储器
公开(公告)号：US09112139B2
公开(公告)日：2015-08-18
申请号：US13526007
申请日：2012-06-18
申请人： Tomoaki Inokuchi , Takao Marukame , Tetsufumi Tanamoto , Hideyuki Sugiyama , Mizue Ishikawa , Yoshiaki Saito
发明人： Tomoaki Inokuchi , Takao Marukame , Tetsufumi Tanamoto , Hideyuki Sugiyama , Mizue Ishikawa , Yoshiaki Saito
IPC分类号： H01L43/08 , H01L29/66
CPC分类号： H01L43/08 , H01L29/66984
摘要： A spin transistor according to an embodiment includes: a first magnetic layer formed above a substrate and serving as one of a source and a drain; an insulating film having a lower face facing to an upper face of the first magnetic layer, an upper face opposed to the lower face, and a side face different from the lower and upper faces, the insulating film being formed on the upper face of the first magnetic layer and serving as a channel; a second magnetic layer formed on the upper face of the insulating film and serving as the other one of the source and the drain; a gate electrode formed along the side face of the insulating film; and a gate insulating film located between the gate electrode and the side face of the insulating film.
摘要翻译：根据实施例的自旋晶体管包括：形成在衬底上并用作源极和漏极之一的第一磁性层; 绝缘膜，其具有面向第一磁性层的上表面的下表面，与下表面相对的上表面，以及不同于下表面和上表面的侧面，绝缘膜形成在第一磁性层的上表面上第一磁性层，作为通道; 第二磁性层，形成在绝缘膜的上表面上并用作源极和漏极中的另一个; 沿绝缘膜的侧面形成的栅电极; 以及位于绝缘膜的栅极和侧面之间的栅极绝缘膜。

4. 发明授权

US08373437B2 Look-up table circuits and field programmable gate array 有权
标题翻译：查找表电路和现场可编程门阵列
公开(公告)号：US08373437B2
公开(公告)日：2013-02-12
申请号：US13238020
申请日：2011-09-21
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/177
摘要： A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.
摘要翻译：根据实施例的查找表电路包括：可变电阻电路，包括可变电阻器件，并且基于输入信号从可变电阻器件中选择可变电阻器件; 参考电路，其具有可变电阻电路的最大电阻值和最小电阻值之间的电阻值; 第一n沟道MOSFET，其包括连接到可变电阻电路的端子的源极和连接到漏极的栅极; 第二n沟道MOSFET，其包括连接到参考电路的端子的源极和连接到第一n沟道MOSFET的栅极的栅极; 用于向可变电阻电路提供电流的第一电流供应电路; 第二电流供应电路，用于向参考电路提供电流; 以及比较器，用于比较第一输入端和第二输入端的电压。

5. 发明申请

US20120119274A1 NONVOLATILE MEMORY CIRCUIT USING SPIN MOS TRANSISTORS 有权
标题翻译：使用旋转MOS晶体管的非易失性存储器电路
公开(公告)号：US20120119274A1
公开(公告)日：2012-05-17
申请号：US13360904
申请日：2012-01-30
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： H01L27/22
CPC分类号： G11C14/0081
摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
摘要翻译：某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

6. 发明授权

US08405443B2 Pass transistor circuit with memory function, and switching box circuit including the pass transistor circuit 有权
标题翻译：具有存储功能的晶体管电路，以及包括传输晶体管电路的开关盒电路
公开(公告)号：US08405443B2
公开(公告)日：2013-03-26
申请号：US13419555
申请日：2012-03-14
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： H03K17/687
CPC分类号： H01L27/112 , H03K19/17736
摘要： A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET.
摘要翻译：根据实施例的传输晶体管电路包括：连接到第一信号线的第一输入/输出端子; 连接到第二信号线的第二输入/输出端子; 第一装置，具有连接到第一电源和第二端子的第一端子; 第二装置，具有连接到第二端子的第三端子和连接到第二电源的第四端子; 第一晶体管，其源极/漏极中的一个连接到第二端子，栅极接收第一控制信号; 以及第二晶体管，其栅极连接到第一晶体管的源极/漏极中的另一个，栅极/漏极中的一个连接到第一输入/输出端子，另一个源极/漏极连接到第二输入/输出端终奌站。第一和第二器件中的一个是非易失性存储器件，第一和第二器件中的另一个是MOSFET。

7. 发明申请

US20120223762A1 PASS TRANSISTOR CIRCUIT WITH MEMORY FUNCTION, AND SWITCHING BOX CIRCUIT INCLUDING THE PASS TRANSISTOR CIRCUIT 有权
标题翻译：具有存储器功能的通用晶体管电路，以及包括通过晶体管电路的开关盒电路
公开(公告)号：US20120223762A1
公开(公告)日：2012-09-06
申请号：US13419555
申请日：2012-03-14
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： H03K17/00
CPC分类号： H01L27/112 , H03K19/17736
摘要： A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET.
摘要翻译：根据实施例的传输晶体管电路包括：连接到第一信号线的第一输入/输出端子; 连接到第二信号线的第二输入/输出端子; 第一装置，具有连接到第一电源和第二端子的第一端子; 第二装置，具有连接到第二端子的第三端子和连接到第二电源的第四端子; 第一晶体管，其源极/漏极中的一个连接到第二端子，栅极接收第一控制信号; 以及第二晶体管，其栅极连接到第一晶体管的源极/漏极中的另一个，栅极/漏极中的一个连接到第一输入/输出端子，另一个源极/漏极连接到第二输入/输出端终奌站。第一和第二器件中的一个是非易失性存储器件，第一和第二器件中的另一个是MOSFET。

8. 发明授权

US08611143B2 Memory circuit using spin MOSFETs, path transistor circuit with memory function, switching box circuit, switching block circuit, and field programmable gate array 有权
标题翻译：使用自旋MOSFET的存储电路，具有存储功能的路径晶体管电路，开关盒电路，开关块电路和现场可编程门阵列
公开(公告)号：US08611143B2
公开(公告)日：2013-12-17
申请号：US13403308
申请日：2012-02-23
申请人： Hideyuki Sugiyama , Masato Oda , Shinobu Fujita , Tetsufumi Tanamoto , Mizue Ishikawa , Takao Marukame , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Masato Oda , Shinobu Fujita , Tetsufumi Tanamoto , Mizue Ishikawa , Takao Marukame , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： G11C11/00
CPC分类号： G11C5/148 , G11C11/161 , G11C11/1673 , G11C11/1675
摘要： A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal.
摘要翻译：根据实施例的存储器电路包括：第一晶体管，包括第一源极/漏极，第二源极/漏极和第一栅电极; 第二晶体管，包括连接到第二源极/漏极的第三源极/漏极，第四源极/漏极和第二栅极; 第三晶体管和形成逆变器电路的第四晶体管，所述第三晶体管包括第五源极/漏极，第六源极/漏极和连接到所述第二源极/漏极的第三栅电极，所述第四晶体管包括第七连接到第六源极/漏极的源极/漏极电极，连接到第二源极/漏极的第八源极/漏极电极和第四栅极电极; 以及连接到第六源极/漏极的输出端子。第三晶体管和第四晶体管中的至少一个是自旋MOSFET，并且从输出端子发送反相器电路的输出。

9. 发明申请

US20130075843A1 SPIN TRANSISTOR AND MEMORY 有权
标题翻译：旋转晶体管和存储器
公开(公告)号：US20130075843A1
公开(公告)日：2013-03-28
申请号：US13526007
申请日：2012-06-18
申请人： Tomoaki Inokuchi , Takao Marukame , Tetsufumi Tanamoto , Hideyuki Sugiyama , Mizue Ishikawa , Yoshiaki Saito
发明人： Tomoaki Inokuchi , Takao Marukame , Tetsufumi Tanamoto , Hideyuki Sugiyama , Mizue Ishikawa , Yoshiaki Saito
IPC分类号： H01L29/82
CPC分类号： H01L43/08 , H01L29/66984
摘要： A spin transistor according to an embodiment includes: a first magnetic layer formed above a substrate and serving as one of a source and a drain; an insulating film having a lower face facing to an upper face of the first magnetic layer, an upper face opposed to the lower face, and a side face different from the lower and upper faces, the insulating film being formed on the upper face of the first magnetic layer and serving as a channel; a second magnetic layer formed on the upper face of the insulating film and serving as the other one of the source and the drain; a gate electrode formed along the side face of the insulating film; and a gate insulating film located between the gate electrode and the side face of the insulating film.
摘要翻译：根据实施例的自旋晶体管包括：形成在衬底上并用作源极和漏极之一的第一磁性层; 绝缘膜，其具有面向第一磁性层的上表面的下表面，与下表面相对的上表面，以及不同于下表面和上表面的侧面，绝缘膜形成在第一磁性层的上表面上第一磁性层，作为通道; 第二磁性层，形成在绝缘膜的上表面上并用作源极和漏极中的另一个; 沿绝缘膜的侧面形成的栅电极; 以及位于绝缘膜的栅极和侧面之间的栅极绝缘膜。

10. 发明授权

US08385114B2 Nonvolatile memory circuit using spin MOS transistors 有权
标题翻译：使用自旋MOS晶体管的非易失性存储电路
公开(公告)号：US08385114B2
公开(公告)日：2013-02-26
申请号：US13360904
申请日：2012-01-30
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： G11C11/14
CPC分类号： G11C14/0081
摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
摘要翻译：某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

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