专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08406028B1 Word line layout for semiconductor memory 有权
标题翻译：半导体存储器的字线布局
公开(公告)号：US08406028B1
公开(公告)日：2013-03-26
申请号：US13285212
申请日：2011-10-31
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Ping-Wei Wang , Huai-Ying Huang
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Ping-Wei Wang , Huai-Ying Huang
IPC分类号： G11C5/06 , H01L21/66
CPC分类号： H01L27/1104 , G11C8/16 , G11C11/412 , H01L27/0207
摘要： A semiconductor memory includes first and second word lines. A first bit cell of a first type is coupled to a first one of a plurality of bit lines and has a first layout in which the first bit cell of the first type is coupled to the first word line with a first number of vias and to the second word line with a second number of vias. A first bit cell of a second type is coupled to a second one of the plurality of bit lines and has a second layout in which the first bit cell of the second type is coupled to the first word line with a third number of vias and to the second word line with a fourth number of vias. A load on the first word line is approximately equal to a load on the second word line.
摘要翻译：半导体存储器包括第一和第二字线。第一类型的第一位单元耦合到多个位线中的第一位，并且具有第一布局，其中第一类型的第一位单元与第一数量的通孔耦合到第一字线，并且第二个字线与第二个通孔。第二类型的第一位单元耦合到多个位线中的第二位，并且具有第二布局，其中第二类型的第一位单元与第三数量的通孔耦合到第一字线，并且第二个字线，第四个通孔。第一个字线上的负载近似等于第二个字线上的负载。

2. 发明授权

US07466581B2 SRAM design with separated VSS 有权
公开(公告)号：US07466581B2
公开(公告)日：2008-12-16
申请号：US11713280
申请日：2007-03-02
申请人： Huai-Ying Huang , Yen-Huei Chen , Jui-Jen Wu , Ping-Wei Wang
发明人： Huai-Ying Huang , Yen-Huei Chen , Jui-Jen Wu , Ping-Wei Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other.

3. 发明申请

US20080212353A1 SRAM design with separated VSS 有权
标题翻译： SRAM设计与VSS分离
公开(公告)号：US20080212353A1
公开(公告)日：2008-09-04
申请号：US11713280
申请日：2007-03-02
申请人： Huai-Ying Huang , Yen-Huei Chen , Jui-Jen Wu , Ping-Wei Wang
发明人： Huai-Ying Huang , Yen-Huei Chen , Jui-Jen Wu , Ping-Wei Wang
IPC分类号： G11C5/06
CPC分类号： G11C11/413
摘要： An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other.
摘要翻译：布置在多行和多列中的静态随机存取存储器（SRAM）单元的阵列包括连接到SRAM单元的VSS节点的多条VSS线，每条VSS线连接到同一列中的SRAM单元。多个VSS线包括连接到SRAM单元的第一列的第一VSS线; 以及连接到所述SRAM单元的第二列的第二VSS线，其中所述第一和第二VSS线彼此断开。

4. 发明授权

US08642451B2 Active region patterning in double patterning processes 有权
标题翻译：双重图案化工艺中的有源区域图案化
公开(公告)号：US08642451B2
公开(公告)日：2014-02-04
申请号：US12917205
申请日：2010-11-01
申请人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang , Hsiang-Lin Chen
发明人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang , Hsiang-Lin Chen
IPC分类号： H01L21/20
CPC分类号： H01L27/1104 , H01L27/0207
摘要： A method includes forming an SRAM cell including a first and a second pull-up transistor and a first and a second pull-down transistor. The step of forming the SRAM cell includes forming a first and a second active region of the first and the second pull-up transistors using a first lithography mask, and forming a third and a fourth active region of the first and the second pull-down transistors using a second lithography mask.
摘要翻译：一种方法包括形成包括第一和第二上拉晶体管以及第一和第二下拉晶体管的SRAM单元。形成SRAM单元的步骤包括使用第一光刻掩模形成第一和第二上拉晶体管的第一和第二有源区，并且形成第一和第二下拉的第三和第四有源区使用第二光刻掩模的晶体管。

5. 发明授权

US08330227B2 Integrated semiconductor structure for SRAM and fabrication methods thereof 有权
标题翻译：用于SRAM的集成半导体结构及其制造方法
公开(公告)号：US08330227B2
公开(公告)日：2012-12-11
申请号：US12706809
申请日：2010-02-17
申请人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
发明人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
IPC分类号： H01L21/70
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L27/11 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/7848
摘要： A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.
摘要翻译：提供了具有金属栅极晶体管的SRAM器件。 SRAM器件在衬底上包括PMOS结构和NMOS结构。 PMOS和NMOS结构中的每一个包括p型金属功函数层和n型金属功函数层。 p型工作金属功能层和n型金属功函数层形成PMOS和NMOS结构的组合功函数。

6. 发明授权

US08315085B1 SRAM timing tracking circuit 有权
标题翻译： SRAM定时跟踪电路
公开(公告)号：US08315085B1
公开(公告)日：2012-11-20
申请号：US13289030
申请日：2011-11-04
申请人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang
发明人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang
IPC分类号： G11C11/00
CPC分类号： G11C29/24 , G11C11/41 , G11C29/50012
摘要： A timing tracking circuit is configured within a functional memory array, obviating the need for a separate, standalone timing tracking circuit. A generated pulse is routed circuitously through conductors enlisted for timing purposes, to trigger switching of a test cell in the array, which discharges an associated bit line from a pre-charged high value. The pulled down signal resulting from the discharge is detected at a measurement unit to infer timing characteristics of the memory array. The timing tracking circuitry is implemented by re-purposing certain conductors, test cells and dummy cells inserting certain conductive or nonconductive regions at one or more layers or at vias between layers to alter operation of the respective conductors and cells. Cells and conductors not enlisted for timing remain available for efficient, reliable memory access performance.
摘要翻译：定时跟踪电路配置在功能存储器阵列内，消除了对单独的独立定时跟踪电路的需要。所产生的脉冲通过定时目的的导体被路由布线，以触发阵列中的测试单元的切换，该预定电荷从预充电的高值放电相关联的位线。在测量单元处检测由放电产生的下拉信号以推断存储器阵列的定时特性。定时跟踪电路通过重新使用某些导体，测试单元和虚设单元来实现，所述导体，测试单元和虚设单元在层之间或层之间的通孔处插入某些导电或非导电区域，以改变相应导体和单元的操作。不用于定时的单元和导体仍然可用于高效，可靠的存储器访问性能。

7. 发明申请

US20120108036A1 Active Region Patterning in Double Patterning Processes 有权
标题翻译：双重图案化过程中的活动区域图案化
公开(公告)号：US20120108036A1
公开(公告)日：2012-05-03
申请号：US12917205
申请日：2010-11-01
申请人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang , Hsiang-Lin Chen
发明人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang , Hsiang-Lin Chen
IPC分类号： H01L21/20
CPC分类号： H01L27/1104 , H01L27/0207
摘要： A method includes forming an SRAM cell including a first and a second pull-up transistor and a first and a second pull-down transistor. The step of forming the SRAM cell includes forming a first and a second active region of the first and the second pull-up transistors using a first lithography mask, and forming a third and a fourth active region of the first and the second pull-down transistors using a second lithography mask.
摘要翻译：一种方法包括形成包括第一和第二上拉晶体管以及第一和第二下拉晶体管的SRAM单元。形成SRAM单元的步骤包括使用第一光刻掩模形成第一和第二上拉晶体管的第一和第二有源区，并且形成第一和第二下拉的第三和第四有源区使用第二光刻掩模的晶体管。

8. 发明授权

US08441829B2 Stable SRAM cell 有权
公开(公告)号：US08441829B2
公开(公告)日：2013-05-14
申请号：US12727985
申请日：2010-03-19
申请人： Huai-Ying Huang , Yu-Kuan Lin , Sheng Chiang Hung , Feng-Ming Chang , Jui-Lin Chen , Ping-Wei Wang
发明人： Huai-Ying Huang , Yu-Kuan Lin , Sheng Chiang Hung , Feng-Ming Chang , Jui-Lin Chen , Ping-Wei Wang
IPC分类号： G11C15/00
CPC分类号： G11C11/412 , G11C11/419
摘要： SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

9. 发明申请

US20110198699A1 INTEGRATED SEMICONDUCTOR STRUCTURE FOR SRAM AND FABRICATION METHODS THEREOF 有权
标题翻译：用于SRAM及其制造方法的集成半导体结构
公开(公告)号：US20110198699A1
公开(公告)日：2011-08-18
申请号：US12706809
申请日：2010-02-17
申请人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
发明人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L27/11 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/7848
摘要： A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.
摘要翻译：提供了具有金属栅极晶体管的SRAM器件。 SRAM器件在衬底上包括PMOS结构和NMOS结构。 PMOS和NMOS结构中的每一个包括p型金属功函数层和n型金属功函数层。 p型工作金属功能层和n型金属功函数层形成PMOS和NMOS结构的组合功函数。

10. 发明授权

US08940589B2 Well implant through dummy gate oxide in gate-last process 有权
标题翻译：通过伪栅极氧化物在栅极 - 最后工艺中注入
公开(公告)号：US08940589B2
公开(公告)日：2015-01-27
申请号：US12789780
申请日：2010-05-28
申请人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
发明人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
IPC分类号： H01L21/84 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/7836 , H01L21/823807 , H01L21/823892 , H01L29/0847 , H01L29/167 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/6659
摘要： The present disclosure relates to methods for fabricating a field-effect transistor. The method includes performing a pocket implantation to a semiconductor substrate; thereafter forming a polysilicon layer on the semiconductor substrate; and patterning the polysilicon layer to form a polysilicon gate.The field-effect transistor (FET) includes a well of a first type dopant, formed in a semiconductor substrate; a metal gate disposed on the semiconductor substrate and overlying the well; a channel formed in the semiconductor substrate and underlying the metal gate; source and drain regions of a second type dopant opposite from the first type, the source and drain regions being formed in the semiconductor substrate and on opposite sides of the channel; and a pocket doping profile of the first type dopant and being defined in the well to form a continuous and uniform doping region from the source region to the drain region.
摘要翻译：本公开涉及用于制造场效应晶体管的方法。该方法包括对半导体衬底进行袋注入; 然后在半导体衬底上形成多晶硅层; 并构图多晶硅层以形成多晶硅栅极。场效应晶体管（FET）包括形成在半导体衬底中的第一类型掺杂剂的阱; 设置在半导体衬底上并覆盖阱的金属栅极; 形成在半导体衬底中并在金属栅极下方的沟道; 源极和漏极区域形成在半导体衬底中并在沟道的相对侧上;第二类型掺杂物的源极和漏极区域与第一类型相反，以及第一类型掺杂剂的口袋掺杂分布，并且在阱中限定以形成从源极区域到漏极区域的连续且均匀的掺杂区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式