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1. 发明授权

US08406028B1 Word line layout for semiconductor memory 有权
标题翻译：半导体存储器的字线布局
公开(公告)号：US08406028B1
公开(公告)日：2013-03-26
申请号：US13285212
申请日：2011-10-31
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Ping-Wei Wang , Huai-Ying Huang
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Ping-Wei Wang , Huai-Ying Huang
IPC分类号： G11C5/06 , H01L21/66
CPC分类号： H01L27/1104 , G11C8/16 , G11C11/412 , H01L27/0207
摘要： A semiconductor memory includes first and second word lines. A first bit cell of a first type is coupled to a first one of a plurality of bit lines and has a first layout in which the first bit cell of the first type is coupled to the first word line with a first number of vias and to the second word line with a second number of vias. A first bit cell of a second type is coupled to a second one of the plurality of bit lines and has a second layout in which the first bit cell of the second type is coupled to the first word line with a third number of vias and to the second word line with a fourth number of vias. A load on the first word line is approximately equal to a load on the second word line.
摘要翻译：半导体存储器包括第一和第二字线。第一类型的第一位单元耦合到多个位线中的第一位，并且具有第一布局，其中第一类型的第一位单元与第一数量的通孔耦合到第一字线，并且第二个字线与第二个通孔。第二类型的第一位单元耦合到多个位线中的第二位，并且具有第二布局，其中第二类型的第一位单元与第三数量的通孔耦合到第一字线，并且第二个字线，第四个通孔。第一个字线上的负载近似等于第二个字线上的负载。

2. 发明授权

US08773930B2 Built-in test circuit and method 有权
标题翻译：内置测试电路及方法
公开(公告)号：US08773930B2
公开(公告)日：2014-07-08
申请号：US13365631
申请日：2012-02-03
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C29/006 , G11C29/06 , G11C2029/2602
摘要： A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.
摘要翻译：测试半导体存储器的方法包括在封装半导体存储器之前执行第一类型的第一测试。第一类型的第一测试包括产生第一多个地址，解码第一多个地址以在第一解码器处产生第二多个解码地址，以及激活半导体的多个行或多个列中的一个基于第二多个解码地址的存储器。在执行第一类型的第一测试之后封装半导体存储器。

3. 发明申请

US20130201776A1 BUILT-IN TEST CIRCUIT AND METHOD 有权
标题翻译：内置测试电路和方法
公开(公告)号：US20130201776A1
公开(公告)日：2013-08-08
申请号：US13365631
申请日：2012-02-03
申请人： Tzu-Kuei LIN , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
发明人： Tzu-Kuei LIN , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C29/006 , G11C29/06 , G11C2029/2602
摘要： A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.
摘要翻译：测试半导体存储器的方法包括在封装半导体存储器之前执行第一类型的第一测试。第一类型的第一测试包括产生第一多个地址，解码第一多个地址以在第一解码器处产生第二多个解码地址，以及激活半导体的多个行或多个列中的一个基于第二多个解码地址的存储器。在执行第一类型的第一测试之后封装半导体存储器。

4. 发明授权

US08693265B2 Data inversion for dual-port memory 有权
标题翻译：双端口存储器的数据反转
公开(公告)号：US08693265B2
公开(公告)日：2014-04-08
申请号：US13552692
申请日：2012-07-19
申请人： Tzu-Kuei Lin , Jonathan Tsung-Yung Chang , Hung-Jen Liao , Yen-Huei Chen , Jhon Jhy Liaw
发明人： Tzu-Kuei Lin , Jonathan Tsung-Yung Chang , Hung-Jen Liao , Yen-Huei Chen , Jhon Jhy Liaw
IPC分类号： G11C16/04
CPC分类号： G11C7/1006 , G11C7/1075 , G11C8/16 , G11C11/412
摘要： A semiconductor memory includes first and second memory storage latches each including first and second ports. A first pair of bit lines is coupled to the first ports, and a second pair of bit lines is coupled to the second ports. The first and second pairs of bit lines are twisted between the first and second memory storage latches. A first sense amplifier is coupled to the first pair of bit lines for outputting data, and a second sense amplifier is coupled to the second pair of bit lines for outputting an intermediate data signal. Output logic circuitry is coupled to an output of the second sense amplifier and is configured to output data based on the intermediate data signal and a control signal that identifies if the data is being read from the first memory storage latch or from the second memory storage latch.
摘要翻译：半导体存储器包括每个包括第一和第二端口的第一和第二存储器存储器锁存器。第一对位线耦合到第一端口，并且第二对位线耦合到第二端口。第一和第二对位线在第一和第二存储器锁存器之间被扭转。第一读出放大器耦合到第一对位线，用于输出数据，第二读出放大器耦合到第二对位线，用于输出中间数据信号。输出逻辑电路耦合到第二读出放大器的输出，并且被配置为基于中间数据信号和控制信号输出数据，该控制信号识别数据是否正在从第一存储器存储锁存器或第二存储器存储器锁存器中读取。

5. 发明授权

US09099199B2 Memory cell and memory array 有权
标题翻译：存储单元和存储器阵列
公开(公告)号：US09099199B2
公开(公告)日：2015-08-04
申请号：US13420931
申请日：2012-03-15
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Jhon Jhy Liaw , Yen-Huei Chen
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Jhon Jhy Liaw , Yen-Huei Chen
IPC分类号： G11C11/00 , G11C11/412
CPC分类号： G11C11/41 , G11C11/412
摘要： A memory cell includes a first, second, and third columns of devices. The first column of devices includes a first pull-down transistor, a second pull-down transistor, a first switch, and a second switch. The second column of devices includes a third pull-down transistor, a fourth pull-down transistor, a third switch, and a fourth switch. The third column of devices includes a first pull-up transistor, and a second pull-up transistor. The first pull-up transistor, the first pull-down transistor, and the third pull-down transistor are connected as a first inverter, and the second pull-up transistor, the second pull-down transistor, and the fourth pull-down transistor are connected as a second inverter. The first inverter and the second inverter are cross-coupled. The first switch, the second switch, the third switch, and the fourth switch are coupled with output terminals of the first and second inverters.
摘要翻译：存储器单元包括第一，第二和第三列器件。第一列器件包括第一下拉晶体管，第二下拉晶体管，第一开关和第二开关。第二列器件包括第三下拉晶体管，第四下拉晶体管，第三开关和第四开关。第三列器件包括第一上拉晶体管和第二上拉晶体管。第一上拉晶体管，第一下拉晶体管和第三下拉晶体管作为第一反相器连接，第二上拉晶体管，第二下拉晶体管和第四下拉晶体管作为第二反相器连接。第一个反相器和第二个反相器是交叉耦合的。第一开关，第二开关，第三开关和第四开关与第一和第二逆变器的输出端子耦合。

6. 发明授权

US07466581B2 SRAM design with separated VSS 有权
公开(公告)号：US07466581B2
公开(公告)日：2008-12-16
申请号：US11713280
申请日：2007-03-02
申请人： Huai-Ying Huang , Yen-Huei Chen , Jui-Jen Wu , Ping-Wei Wang
发明人： Huai-Ying Huang , Yen-Huei Chen , Jui-Jen Wu , Ping-Wei Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other.

7. 发明申请

US20080212353A1 SRAM design with separated VSS 有权
标题翻译： SRAM设计与VSS分离
公开(公告)号：US20080212353A1
公开(公告)日：2008-09-04
申请号：US11713280
申请日：2007-03-02
申请人： Huai-Ying Huang , Yen-Huei Chen , Jui-Jen Wu , Ping-Wei Wang
发明人： Huai-Ying Huang , Yen-Huei Chen , Jui-Jen Wu , Ping-Wei Wang
IPC分类号： G11C5/06
CPC分类号： G11C11/413
摘要： An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other.
摘要翻译：布置在多行和多列中的静态随机存取存储器（SRAM）单元的阵列包括连接到SRAM单元的VSS节点的多条VSS线，每条VSS线连接到同一列中的SRAM单元。多个VSS线包括连接到SRAM单元的第一列的第一VSS线; 以及连接到所述SRAM单元的第二列的第二VSS线，其中所述第一和第二VSS线彼此断开。

8. 发明授权

US09041069B2 Distributed metal routing 有权
标题翻译：分布式金属布线
公开(公告)号：US09041069B2
公开(公告)日：2015-05-26
申请号：US13007235
申请日：2011-01-14
申请人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
发明人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L23/485 , H01L23/528 , H01L23/482 , H01L23/522
CPC分类号： H01L21/76879 , H01L21/768 , H01L21/76832 , H01L23/4824 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
摘要翻译：公开了一种用于分布式金属布线的系统和方法。一个实施例包括具有覆盖在metal_0层上的metal_1层的metal_0层。金属层1包括分开的平行线，具有不同信号的线分布在metal_1层上。这样的布局减小了metal_0层内的寄生电阻，因为它减小了电流行进的距离。此外，metal_1中的分布式布局允许连接到metal_2层，而不需要通孔的锤头连接。

9. 发明申请

US20130263066A1 Pre-Colored Methodology of Multiple Patterning 有权
标题翻译：多种图案预色彩方法
公开(公告)号：US20130263066A1
公开(公告)日：2013-10-03
申请号：US13607946
申请日：2012-09-10
申请人： Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
发明人： Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Some embodiments relate to a method of pre-coloring word lines and control lines within an SRAM integrated chip design to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The method is performed by generating a graphical IC layout file having an SRAM circuit with a plurality of word lines and Y-control lines. The word lines and Y-control lines are assigned a color during decomposition. The word lines and Y-control lines are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. Therefore, during mask building, data associated with pre-colored word and Y-control lines is sent to a same mask, regardless of the colors that are assigned to the data. By assigning word and Y-control lines to a same mask through pre-coloring, processing variations between the word and Y-control lines are minimized, thereby mitigating timing variations in an SRAM circuit.
摘要翻译：一些实施例涉及在SRAM集成芯片设计中预先着色字线和控制线的方法，以避免由通过多次图案化光刻工艺引入的处理变化而产生的定时延迟。该方法通过生成具有多个字线和Y控制线的SRAM电路的图形IC布局文件来执行。在分解过程中，字线和Y控制线被分配一个颜色。字线和Y控制线进一步预先着色，以故意将预色数据分配给相同的掩码。因此，在面具构建期间，与预色彩字和Y控制线相关联的数据被发送到相同的掩码，而不管分配给数据的颜色如何。通过预分色将字和Y控制线分配给相同的掩码，字和Y控制线之间的处理变化被最小化，从而减轻SRAM电路中的定时变化。

10. 发明授权

US08363454B2 SRAM bit cell 有权
标题翻译： SRAM位单元
公开(公告)号：US08363454B2
公开(公告)日：2013-01-29
申请号：US13015773
申请日：2011-01-28
申请人： Ping Wang , Hung-Jen Liao , Yen-Huei Chen , Jihi-Yu Lin , Shao-Yu Chou
发明人： Ping Wang , Hung-Jen Liao , Yen-Huei Chen , Jihi-Yu Lin , Shao-Yu Chou
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A semiconductor memory bit cell includes an inverter latch including a pair of cross-coupled inverters. A first transistor has a gate coupled to a first control line and a source coupled to the inverter latch, and a second transistor has a gate coupled to a second control line and a drain coupled to the drain of the first transistor at a first node. A third transistor has a source coupled to the first node and a gate coupled to a word line, and a fourth transistor has a gate coupled to a source of the second transistor and to the inverter latch. A fifth transistor has a gate coupled to the word line and a drain coupled to a read bit line.
摘要翻译：半导体存储器位单元包括具有一对交叉耦合的反相器的反相器锁存器。第一晶体管具有耦合到第一控制线的栅极和耦合到反相器锁存器的源极，并且第二晶体管具有耦合到第二控制线的栅极和在第一节点耦合到第一晶体管的漏极的漏极。第三晶体管具有耦合到第一节点的源极和耦合到字线的栅极，并且第四晶体管具有耦合到第二晶体管的源极和反相器锁存器的栅极。第五晶体管具有耦合到字线的栅极和耦合到读位线的漏极。

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