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1. 发明授权

US09806130B2 Memory element with a reactive metal layer 有权
公开(公告)号：US09806130B2
公开(公告)日：2017-10-31
申请号：US15393545
申请日：2016-12-29
申请人： UNITY SEMICONDUCTOR CORPORATION
发明人： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F. S. Swab , Edmond R. Ward
IPC分类号： H01L45/00 , G11C11/56 , H01L27/24 , G11C13/00
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

2. 发明申请

US20140219006A1 ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY 有权
标题翻译：交叉点信息调整电路和存储单元的方法
公开(公告)号：US20140219006A1
公开(公告)日：2014-08-07
申请号：US14150521
申请日：2014-01-08
申请人： Unity Semiconductor Corporation
发明人： Christophe J. Chevallier , Chang Hua Siau
IPC分类号： G11C13/00
CPC分类号： G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地涉及系统，集成电路和方法，用于产生存取信号以促进存储器元件的按比例排列的存储器操作，诸如在形成的第三维存储器技术中实现的存储器直接位于包含数据访问电路的FEOL基板之上。在至少一些实施例中，非易失性存储器件可以包括具有布置在字线和位线子集之间的电阻性存储器元件的交叉点阵列和存取信号发生器。访问信号发生器可以被配置为修改信号的大小以产生用于信号的修改的幅度，以访问与字线和位线的子集相关联的电阻性存储器元件。修改的幅度可以是交叉点阵列中的电阻性存储元件的位置的函数。

3. 发明申请

US20180130946A1 TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE 审中-公开
公开(公告)号：US20180130946A1
公开(公告)日：2018-05-10
申请号：US15797452
申请日：2017-10-30
申请人： Unity Semiconductor Corporation
发明人： Darrell Rinerson , Christophe J. Chevallier , Wayne Kinney , Roy Lambertson , John E. Sanchez, JR. , Lawrence Schloss , Philip Swab , Edmond Ward
IPC分类号： H01L45/00 , G06F17/50 , H01L27/24 , G11C11/56 , G11C13/00
CPC分类号： H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
摘要： A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

4. 发明申请

US20180122857A1 MEMORY ELEMENT WITH A REACTIVE METAL LAYER 审中-公开
公开(公告)号：US20180122857A1
公开(公告)日：2018-05-03
申请号：US15797716
申请日：2017-10-30
申请人： UNITY SEMICONDUCTOR CORPORATION
发明人： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F.S. Swab , Edmond R. Ward
IPC分类号： H01L27/24 , H01L45/00 , G11C11/56 , G11C11/16 , G11C13/00
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

5. 发明申请

US20170179197A1 MEMORY ELEMENT WITH A REACTIVE METAL LAYER 有权
公开(公告)号：US20170179197A1
公开(公告)日：2017-06-22
申请号：US15393545
申请日：2016-12-29
申请人： UNITY SEMICONDUCTOR CORPORATION
发明人： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F.S. Swab , Edmond R. Ward
IPC分类号： H01L27/24 , G11C13/00 , H01L45/00
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

6. 发明申请

US20170162261A1 PRESERVATION CIRCUIT AND METHODS TO MAINTAIN VALUES REPRESENTING DATA IN ONE OR MORE LAYERS OF MEMORY 有权
公开(公告)号：US20170162261A1
公开(公告)日：2017-06-08
申请号：US15381566
申请日：2016-12-16
申请人： UNITY SEMICONDUCTOR CORPORATION
发明人： Christophe J. Chevallier , Robert Norman
IPC分类号： G11C13/00
CPC分类号： G11C13/0035 , G11C5/005 , G11C5/02 , G11C11/16 , G11C13/0002 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/71 , G11C2213/77
摘要： Methods to maintain values representing data in a memory are disclosed. A method may include identifying a plurality of in-use portions of the memory currently used to store data and recording which in-use portion was a last portion of the memory to be rewritten. Responsive to a trigger signal, data is read from a selected one of the in-use portions of the memory adjacent to the last portion. The method may also include storing the read data into a buffer to form buffered data, and rewriting the buffered data into the memory.

7. 发明申请

US20160005793A1 MEMORY ELEMENT WITH A REACTIVE METAL LAYER 有权
标题翻译：具有反应性金属层的记忆元件
公开(公告)号：US20160005793A1
公开(公告)日：2016-01-07
申请号：US14850702
申请日：2015-09-10
申请人： Unity Semiconductor Corporation
发明人： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F.S. Swab , Edmond R. Ward
IPC分类号： H01L27/24 , G11C13/00 , H01L45/00
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
摘要翻译：公开了一种包括导电氧化物电极的存储单元。存储单元包括用于将数据存储为多个电阻状态的存储元件。存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。导电氧化物层也可以与金属层（例如Pt）接触。存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。

8. 发明授权

US09159913B2 Two-terminal reversibly switchable memory device 有权
标题翻译：双端可逆切换存储器件
公开(公告)号：US09159913B2
公开(公告)日：2015-10-13
申请号：US14463518
申请日：2014-08-19
申请人： Unity Semiconductor Corporation
发明人： Darrell Rinerson , Christophe J. Chevallier , Wayne Kinney , Roy Lambertson , John E. Sanchez, Jr. , Lawrence Schloss , Philip Swab , Edmond Ward
IPC分类号： H01L45/00 , G06F17/50 , G11C11/56 , G11C13/00 , H01L27/24
CPC分类号： H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
摘要： A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
摘要翻译：公开了使用混合价态导电氧化物的记忆体。存储器包括在其缺氧状态下导电性较差的混合价态导电氧化物和作为电解质的氧的混合电子离子导体并且促进有效引起氧离子运动的电场。

9. 发明申请

US20150179250A1 ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY 有权
标题翻译：交叉点信息调整电路和存储单元的方法
公开(公告)号：US20150179250A1
公开(公告)日：2015-06-25
申请号：US14624891
申请日：2015-02-18
申请人： Unity Semiconductor Corporation
发明人： Christophe J. Chevallier , Chang Hua Siau
IPC分类号： G11C13/00
CPC分类号： G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地涉及系统，集成电路和方法，用于产生存取信号以促进存储器元件的按比例排列的存储器操作，诸如在形成的第三维存储器技术中实现的存储器直接位于包含数据访问电路的FEOL基板之上。在至少一些实施例中，非易失性存储器件可以包括具有布置在字线和位线子集之间的电阻性存储器元件的交叉点阵列和存取信号发生器。访问信号发生器可被配置为修改信号的大小以产生用于信号访问与字线和位线子集相关联的电阻性存储器元件的修改幅度。修改的幅度可以是交叉点阵列中的电阻性存储元件的位置的函数。

10. 发明授权

US08988930B2 Access signal adjustment circuits and methods for memory cells in a cross-point array 有权
标题翻译：交叉点阵列中存储单元的访问信号调整电路和方法
公开(公告)号：US08988930B2
公开(公告)日：2015-03-24
申请号：US14150521
申请日：2014-01-08
申请人： Unity Semiconductor Corporation
发明人： Christophe J. Chevallier , Chang Hua Siau
IPC分类号： G11C11/00 , G11C13/00 , G11C11/21
CPC分类号： G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地涉及系统，集成电路和方法，用于产生存取信号以促进存储器元件的按比例排列的存储器操作，诸如在形成的第三维存储器技术中实现的存储器直接位于包含数据访问电路的FEOL基板之上。在至少一些实施例中，非易失性存储器件可以包括具有布置在字线和位线子集之间的电阻性存储器元件的交叉点阵列和存取信号发生器。访问信号发生器可被配置为修改信号的大小以产生用于信号访问与字线和位线子集相关联的电阻性存储器元件的修改幅度。修改的幅度可以是交叉点阵列中的电阻性存储元件的位置的函数。

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