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1. 发明授权

US08120977B2 Test method for nonvolatile memory device 失效
标题翻译：非易失性存储器件的测试方法
公开(公告)号：US08120977B2
公开(公告)日：2012-02-21
申请号：US12362441
申请日：2009-01-29
申请人： Wan Seob Lee , Jin Yong Seong
发明人： Wan Seob Lee , Jin Yong Seong
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/56012 , G11C2029/2602 , G11C2029/5602
摘要： A test method for nonvolatile memory devices where, in one aspect of the method, a specific operation mode is selected according to a signal input through a single I/O pin in a period in which a write enable signal is inactivated. The write enable signal or a read enable signal is activated according to the selected operation mode. A plurality of signals is input through the single I/O pin in a period in which the write enable signal is activated. The plurality of signals is output through the single I/O pin in a period in which the read enable signal is activated.
摘要翻译：一种用于非易失性存储器件的测试方法，其中在该方法的一个方面中，根据在写入使能信号被禁止的时段中通过单个I / O引脚输入的信号来选择特定操作模式。写使能信号或读使能信号根据所选择的操作模式被激活。在写使能信号被激活的时间段内，通过单个I / O引脚输入多个信号。在读使能信号被激活的时间段内，多个信号通过单个I / O引脚输出。

2. 发明申请

US20090287972A1 TEST METHOD FOR NONVOLATILE MEMORY DEVICE 失效
标题翻译：非易失性存储器件的测试方法
公开(公告)号：US20090287972A1
公开(公告)日：2009-11-19
申请号：US12362441
申请日：2009-01-29
申请人： Wan Seob LEE , Jin Yong Seong
发明人： Wan Seob LEE , Jin Yong Seong
IPC分类号： G11C29/10 , G06F11/263
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/56012 , G11C2029/2602 , G11C2029/5602
摘要： A test method for nonvolatile memory devices where, in one aspect of the method, a specific operation mode is selected according to a signal input through a single I/O pin in a period in which a write enable signal is inactivated. The write enable signal or a read enable signal is activated according to the selected operation mode. A plurality of signals is input through the single I/O pin in a period in which the write enable signal is activated. The plurality of signals is output through the single I/O pin in a period in which the read enable signal is activated.
摘要翻译：一种用于非易失性存储器件的测试方法，其中在该方法的一个方面中，根据在写入使能信号被禁止的时段中通过单个I / O引脚输入的信号来选择特定操作模式。写使能信号或读使能信号根据所选择的操作模式被激活。在写使能信号被激活的时间段内，通过单个I / O引脚输入多个信号。在读使能信号被激活的时间段内，多个信号通过单个I / O引脚输出。

3. 发明授权

US08125828B2 Page buffer circuit with reduced size and methods for reading and programming data with the same 有权
标题翻译：具有减小尺寸的页面缓冲电路和用于读取和编程数据的方法
公开(公告)号：US08125828B2
公开(公告)日：2012-02-28
申请号：US12409400
申请日：2009-03-23
申请人： Jin Yong Seong , Sam Kyu Won
发明人： Jin Yong Seong , Sam Kyu Won
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C16/3459 , G11C2211/5642
摘要： A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation.
摘要翻译：提供了一种缩小尺寸的页面缓冲电路和用于读取和编程数据的方法。在读取操作中，页缓冲器电路通过交替地使用较高位寄存器或低位寄存器读出数据位，而不管从多级单元读取的数据位是高位还是低位，从而减少电路面积提高了运行性能。

4. 发明授权

US07200044B2 Page buffer circuit with reduced size, and flash memory device having page buffer and program operation method thereof 有权
标题翻译：具有减小尺寸的页面缓冲器电路，以及具有页缓冲器的闪存器件及其编程操作方法
公开(公告)号：US07200044B2
公开(公告)日：2007-04-03
申请号：US11164612
申请日：2005-11-30
申请人： Sam Kyu Won , Jin Yong Seong
发明人： Sam Kyu Won , Jin Yong Seong
IPC分类号： G11C16/06 , G11C16/04 , G11C7/10
CPC分类号： G11C16/08
摘要： The present invention relates to a page buffer circuit with a reduced size, and a flash memory device having the page buffer circuit and program operation method thereof. According to the present invention, a page buffer circuit can perform a program operation of a Multi-Level Cell (MLC) using a data verify circuit even without a data compare circuit. Accordingly, an occupation area can be reduced and the size of a flash memory device can also be reduced.
摘要翻译：本发明涉及一种具有减小尺寸的页面缓冲器电路，以及具有页面缓冲器电路及其编程操作方法的闪速存储器件。根据本发明，即使没有数据比较电路，页面缓冲电路也可以使用数据验证电路来执行多电平单元（MLC）的编程操作。因此，可以减少占用面积，并且还可以减小闪存装置的尺寸。

5. 发明授权

US07881127B2 Nonvolatile memory device and method of testing the same 有权
标题翻译：非易失性存储器件及其测试方法
公开(公告)号：US07881127B2
公开(公告)日：2011-02-01
申请号：US12468384
申请日：2009-05-19
申请人： Jin Yong Seong
发明人： Jin Yong Seong
IPC分类号： G11C7/00
CPC分类号： G11C29/32 , G11C29/1201 , G11C29/48
摘要： A nonvolatile memory device includes a clock input stage configured to receive a clock signal for a test, a control signal output unit configured to output data input-output (IO) control signals according to the clock signal, n number of IO stages for data IO, and n number of storage units connected to the respective n number of IO stages and configured to temporarily store data to be exchanged between the respective n number of IO stages and internal circuits according to the respective data IO control signals. The n number of storage units are further commonly connected to a first IO stage of the n number of IO stages and configured to sequentially input or output data through the first IO stage in a test mode according to the respective data IO control signals.
摘要翻译：非易失性存储器件包括被配置为接收用于测试的时钟信号的时钟输入级，配置为根据时钟信号输出数据输入输出（IO）控制信号的控制信号输出单元，用于数据IO的n个IO级数以及连接到相应的n个IO级的n个存储单元，并且被配置为根据相应的数据IO控制信号临时存储要在相应的n个IO级和内部电路之间交换的数据。 n个存储单元进一步通常连接到n个IO级的第一IO级，并且被配置为根据相应的数据IO控制信号在测试模式中通过第一IO级依次输入或输出数据。

6. 发明申请

US20090185419A1 PAGE BUFFER CIRCUIT WITH REDUCED SIZE AND METHODS FOR READING AND PROGRAMMING DATA WITH THE SAME 有权
标题翻译：具有减小尺寸的页面缓冲器电路和用于读取和编程数据的方法
公开(公告)号：US20090185419A1
公开(公告)日：2009-07-23
申请号：US12409400
申请日：2009-03-23
申请人： Jin Yong Seong , Sam Kyu Won
发明人： Jin Yong Seong , Sam Kyu Won
IPC分类号： G11C16/00 , G11C16/06
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C16/3459 , G11C2211/5642
摘要： A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation.
摘要翻译：提供了一种缩小尺寸的页面缓冲电路和用于读取和编程数据的方法。在读取操作中，页缓冲器电路通过交替地使用较高位寄存器或低位寄存器读出数据位，而不管从多级单元读取的数据位是高位还是低位，从而减少电路面积提高了运行性能。

7. 发明申请

US20080080260A1 PAGE BUFFER CIRCUIT OF MEMORY DEVICE AND PROGRAM METHOD 有权
标题翻译：存储器设备和程序方法的页面缓冲电路
公开(公告)号：US20080080260A1
公开(公告)日：2008-04-03
申请号：US11617331
申请日：2006-12-28
申请人： Jin Yong Seong
发明人： Jin Yong Seong
IPC分类号： G11C7/10 , G11C14/00 , G11C16/04 , G11C11/34
CPC分类号： G11C16/26 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C2216/14
摘要： A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and a LSB verification circuit. The MSB latch is configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, and output an inverted upper sensing data, or store an input data and output an inverted input data. The LSB latch is configured to sense a voltage of the sensing node in response to the control signal, and store and output a lower sensing data, or store and output an input data received through the MSB latch. The data I/O circuit is connected to the MSB latch and a data I/O line, and is configured to perform the input and output of a sensing data or the input and output of a program data.
摘要翻译：包括连接到至少一对位线的多个多电平单元（MLC）的存储器件的页缓冲器电路包括最高有效位（MSB）锁存器，最低有效位（LSB）锁存器，数据I / O电路，反相输出电路，MSB验证电路和LSB校验电路。 MSB锁存器被配置为响应于控制信号感测感测节点的电压并存储较高的感测数据，并且输出反转的上部感测数据，或存储输入数据并输出反相的输入数据。 LSB锁存器被配置为响应于控制信号感测感测节点的电压，并且存储和输出较低的感测数据，或者存储和输出通过MSB锁存器接收的输入数据。数据I / O电路连接到MSB锁存器和数据I / O线，并且被配置为执行感测数据的输入和输出或节目数据的输入和输出。

8. 发明授权

US08279651B2 Memory chip package with efficient data I/O control 有权
标题翻译：具有高效数据I / O控制的内存芯片封装
公开(公告)号：US08279651B2
公开(公告)日：2012-10-02
申请号：US12826518
申请日：2010-06-29
申请人： Jin Yong Seong
发明人： Jin Yong Seong
IPC分类号： G11C5/02 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C2207/105
摘要： A memory chip includes a memory circuit unit configured to include memory cells for storing data, a data input and output (I/O) buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip, a plurality of driver control units configured to generate a plurality of driver addition signals to enable corresponding ones of the data I/O buffer circuits depending on whether a power supply voltage has been received, and a controller configured to generate I/O enable signals for controlling an operation of the data I/O buffer unit.
摘要翻译：存储器芯片包括被配置为包括用于存储数据的存储器单元的存储器电路单元，被配置为包括多个数据I / O缓冲电路的数据输入和输出（I / O）缓冲器单元，其中数据I / O 默认情况下操作缓冲电路以便向存储器芯片输入和输出数据;多个驱动器控制单元，被配置为产生多个驱动器相加信号，以使数据I / O缓冲器电路中的相应数据能够根据是否已经接收到电源电压，并且控制器被配置为产生用于控制数据I / O缓冲器单元的操作的I / O使能信号。

9. 发明授权

US07515484B2 Page buffer circuit of memory device and program method 有权
标题翻译：存储器件的页面缓冲电路和程序方法
公开(公告)号：US07515484B2
公开(公告)日：2009-04-07
申请号：US11617331
申请日：2006-12-28
申请人： Jin Yong Seong
发明人： Jin Yong Seong
IPC分类号： G11C7/10
CPC分类号： G11C16/26 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C2216/14
摘要： A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and a LSB verification circuit. The MSB latch is configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, and output an inverted upper sensing data, or store an input data and output an inverted input data. The LSB latch is configured to sense a voltage of the sensing node in response to the control signal, and store and output a lower sensing data, or store and output an input data received through the MSB latch. The data I/O circuit is connected to the MSB latch and a data I/O line, and is configured to perform the input and output of a sensing data or the input and output of a program data.
摘要翻译：包括连接到至少一对位线的多个多电平单元（MLC）的存储器件的页缓冲器电路包括最高有效位（MSB）锁存器，最低有效位（LSB）锁存器，数据I / O电路，反相输出电路，MSB验证电路和LSB校验电路。 MSB锁存器被配置为响应于控制信号感测感测节点的电压并存储较高的感测数据，并且输出反转的上部感测数据，或存储输入数据并输出反相的输入数据。 LSB锁存器被配置为响应于控制信号感测感测节点的电压，并且存储和输出较低的感测数据，或存储和输出通过MSB锁存器接收的输入数据。数据I / O电路连接到MSB锁存器和数据I / O线，并且被配置为执行感测数据的输入和输出或节目数据的输入和输出。

10. 发明申请

US20080101116A1 MULTI-LEVEL CELL COPYBACK PROGRAM METHOD IN A NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件中的多级单元复制程序方法
公开(公告)号：US20080101116A1
公开(公告)日：2008-05-01
申请号：US11926130
申请日：2007-10-29
申请人： Jin Yong Seong , Seong Je Park
发明人： Jin Yong Seong , Seong Je Park
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A multi-level cell copyback program method in a non-volatile memory device is disclosed. The method includes reading LSB data of a source page, and storing the read LSB data in a second register of a page buffer, transmitting the data stored in the second register to a first register coupled to a data inputting circuit, and storing the transmitted data in the first register, amending the data stored in the first register through the data inputting circuit, transmitting the amended data to the second register, and storing the transmitted data in the second register, and LSB-programming corresponding data to a target page in accordance with the data stored in the second register.
摘要翻译：公开了一种在非易失性存储器件中的多级单元复制程序方法。该方法包括读取源页的LSB数据，并将读出的LSB数据存储在页缓冲器的第二寄存器中，将存储在第二寄存器中的数据发送到耦合到数据输入电路的第一寄存器，并存储发送数据在第一寄存器中，通过数据输入电路对存储在第一寄存器中的数据进行修改，将修正的数据发送到第二寄存器，并将发送的数据存储在第二寄存器中，并且将对应数据LSB编程到目标页面数据存储在第二个寄存器中。

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