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1. 发明授权

US07920621B2 Digital adaptation circuitry and methods for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的数字适配电路和方法
公开(公告)号：US07920621B2
公开(公告)日：2011-04-05
申请号：US11522284
申请日：2006-09-14
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

2. 发明授权

US08208523B2 Digital adaptation circuitry and methods for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的数字适配电路和方法
公开(公告)号：US08208523B2
公开(公告)日：2012-06-26
申请号：US13079420
申请日：2011-04-04
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

3. 发明申请

US20110188564A1 DIGITAL ADAPTATION CIRCUITRY AND METHODS FOR PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：数字适配电路和可编程逻辑器件的方法
公开(公告)号：US20110188564A1
公开(公告)日：2011-08-04
申请号：US13079420
申请日：2011-04-04
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03K5/125 , H03K5/19
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

4. 发明申请

US20080069276A1 Digital adaptation circuitry and methods for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的数字适配电路和方法
公开(公告)号：US20080069276A1
公开(公告)日：2008-03-20
申请号：US11522284
申请日：2006-09-14
申请人： Wilson Wong , Doris Po Ching Chan , Simardeep Maangat , Sergey Shumarayev , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Simardeep Maangat , Sergey Shumarayev , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H04B1/10
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

5. 发明授权

US07782935B1 Half-rate DFE with duplicate path for high data-rate operation 有权
标题翻译：具有高数据速率操作的重复路径的半速率DFE
公开(公告)号：US07782935B1
公开(公告)日：2010-08-24
申请号：US11514490
申请日：2006-08-31
申请人： Wilson Wong , Sergey Yuryevich Shumarayev , Simardeep Maangat , Thungoc M. Tran , Tim Tri Hoang , Tin H. Lai
发明人： Wilson Wong , Sergey Yuryevich Shumarayev , Simardeep Maangat , Thungoc M. Tran , Tim Tri Hoang , Tin H. Lai
IPC分类号： H03H7/30
CPC分类号： H03H11/26 , H04L25/03878 , H04L2025/0349
摘要： Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1/n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.
摘要翻译：提出了用于向高数据速率信号提供均衡的方法和电路，包括判决反馈均衡（DFE）。半速率延迟链电路使用以输入信号数据速率的一小部分工作的两个或多个延迟链电路产生输入信号的延迟采样。可以使用以输入信号数据速率的一半工作的两个延迟链电路。更一般地，可以使用以1 / n输入信号数据速率工作的n个延迟链电路。多路复用器电路组合延迟链电路的输出以产生包括输入信号数据速率的输入信号样本的输出信号。重复路径DFE电路包括用于提供DFE均衡的两个路径，同时减少DFE电路之前的电路上的DFE电路的负载。第一路径产生DFE信号的延迟采样，而第二路径产生来自延迟采样的DFE输出信号。

6. 发明授权

US07760799B2 Programmable digital equalization control circuitry and methods 失效
标题翻译：可编程数字均衡控制电路和方法
公开(公告)号：US07760799B2
公开(公告)日：2010-07-20
申请号：US11238365
申请日：2005-09-28
申请人： Tin H. Lai , Sergey Shumarayev , Simardeep Maangat , Wilson Wong
发明人： Tin H. Lai , Sergey Shumarayev , Simardeep Maangat , Wilson Wong
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H03G3/3089 , H04L25/03885
摘要： Equalization circuitry may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages that control the amount of gain provided to the data signal. A comparator may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters. These analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain.
摘要翻译：均衡电路可用于补偿由传输介质引起的数据信号的衰减。用于均衡电路的控制电路可以产生用于控制提供给数据信号的增益量的均衡级的控制输入。比较器可以确定来自均衡电路的增益是否小于或大于期望的增益量。可编程上/下计数器可以根据比较器的输出来调整计数器值。可以使用一个或多个数模转换器将计数器值转换成一个或多个模拟电压。这些模拟电压可以作为控制输入提供给均衡级。控制电路还可以包括滞后电路，当由均衡级产生的增益接近期望的增益量时，阻止计数器值被调整。

7. 发明授权

US07514968B1 H-tree driver circuitry 有权
标题翻译： H树驱动电路
公开(公告)号：US07514968B1
公开(公告)日：2009-04-07
申请号：US11786295
申请日：2007-04-10
申请人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Tim Tri Hoang
发明人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Tim Tri Hoang
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H04L25/0272
摘要： An H-tree driver circuit has pull-up and pull-down current sources, each of which is implemented using a low-voltage-cascode topology.
摘要翻译： H-tree驱动电路具有上拉和下拉电流源，每个都使用低压共源共栅拓扑来实现。

8. 发明授权

US08175143B1 Adaptive equalization using data level detection 有权
标题翻译：使用数据级检测的自适应均衡
公开(公告)号：US08175143B1
公开(公告)日：2012-05-08
申请号：US12037284
申请日：2008-02-26
申请人： Wilson Wong , Tin H. Lai , Allen Chan , Tim Tri Hoang , Sergey Shumarayev
发明人： Wilson Wong , Tin H. Lai , Allen Chan , Tim Tri Hoang , Sergey Shumarayev
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L25/03885 , H04L2025/03356 , H04L2025/03745 , H04L2025/03783
摘要： A method, and circuitry, for choosing the correct equalization curve in adaptive equalization uses a feedback loop in which the incoming high-speed serial data are digitized and deserialized for use in the remainder of the device, and also are used by an adaptive state machine to both extract the reference levels for digitization and to control the equalization curve. Detection of the reference level and selection of the equalization curve may be performed at a different rates to avoid interfering with one another. The state machine preferably is programmable. This is useful in any device, but is particularly well-suited for a programmable device, such as a PLD or other programmable integrated circuit device, where conditions may vary according a user logic design.
摘要翻译：用于在自适应均衡中选择正确的均衡曲线的方法和电路使用反馈回路，其中输入的高速串行数据被数字化和反序列化以用于设备的其余部分，并且还被自适应状态机以提取用于数字化的参考电平并控制均衡曲线。参考电平的检测和均衡曲线的选择可以以不同的速率进行，以避免彼此干扰。状态机优选是可编程的。这在任何设备中是有用的，但是特别适用于诸如PLD或其他可编程集成电路设备的可编程设备，其中条件可以根据用户逻辑设计而变化。

9. 发明授权

US07733997B2 Signal adjustment receiver circuitry 有权
标题翻译：信号调节接收器电路
公开(公告)号：US07733997B2
公开(公告)日：2010-06-08
申请号：US11486581
申请日：2006-07-14
申请人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Simardeep Maangat
发明人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Simardeep Maangat
IPC分类号： H04B1/10
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies. For low frequency adjustment, user-programmable parameters control the normalized signal amplitude in the signal normalization block and the low frequency adjustment in the equalization block.
摘要翻译：公开了一种用于调整从通信路径接收的信号的系统和方法。接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。在一个实施例中，控制块控制用于高频的均衡块中的频率调整。对于低频调整，用户可编程参数控制信号归一化块中的归一化信号幅度和均衡块中的低频调整。

10. 发明授权

US08416898B1 Techniques for decision feedback equalization that reduce variations in the tap weight 有权
标题翻译：用于决策反馈均衡的技术，可减少抽头重量的变化
公开(公告)号：US08416898B1
公开(公告)日：2013-04-09
申请号：US12483151
申请日：2009-06-11
申请人： Mei Luo , Thungoc M. Tran , Tim Tri Hoang , Tin H. Lai
发明人： Mei Luo , Thungoc M. Tran , Tim Tri Hoang , Tin H. Lai
IPC分类号： H04B1/10
CPC分类号： H04L25/03057 , H04L2025/03592
摘要： A circuit includes a receiver circuit, a decision feedback equalizer circuit, and a control loop circuit. The receiver circuit receives a data signal and generates an input signal in response to the data signal. The decision feedback equalizer circuit includes a tap driver and a first current source coupled to the tap driver. The tap driver drives the input signal based on a tap weight. The control loop circuit varies a current through the first current source based on variations in the input signal to reduce changes in the tap weight that are caused by the variations in the input signal.
摘要翻译：电路包括接收器电路，判决反馈均衡器电路和控制回路电路。接收器电路接收数据信号并响应于数据信号产生输入信号。判决反馈均衡器电路包括抽头驱动器和耦合到抽头驱动器的第一电流源。抽头驱动器根据抽头重量驱动输入信号。控制回路电路基于输入信号的变化改变通过第一电流源的电流，以减少由输入信号的变化引起的抽头重量的变化。

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