专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07779229B2 Method and arrangement for bringing together data on parallel data paths 有权
标题翻译：将数据汇集在并行数据路径上的方法和装置
公开(公告)号：US07779229B2
公开(公告)日：2010-08-17
申请号：US10505028
申请日：2003-02-12
申请人： Wolfram Drescher
发明人： Wolfram Drescher
IPC分类号： G06F7/00
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3885
摘要： A processor arrangement having a strip structure for parallel data processing is configured so that local data from the individual processing units or strips is brought together in a rapid manner. Input data, intermediate data and/or output data from various processing units are linked together in an operation which is at least partially combinatory. The data linking operation is not clock controlled. The linking of the local data from various strips in this manner reduces delays in parallel data processing in the processor arrangement. The combinatory data linking operation can provide an overall data linking outcome within an individual clock cycle.
摘要翻译：具有用于并行数据处理的带状结构的处理器装置被配置为使得来自各个处理单元或条带的本地数据以快速方式汇集在一起。来自各种处理单元的输入数据，中间数据和/或输出数据在至少部分组合的操作中被链接在一起。数据链接操作不受时钟控制。以这种方式链接来自各种条的本地数据减少了处理器布置中并行数据处理的延迟。组合数据链接操作可以在单个时钟周期内提供整体数据链接结果。

2. 发明授权

US07647445B2 Processor bus arrangement 有权
标题翻译：处理器总线布置
公开(公告)号：US07647445B2
公开(公告)日：2010-01-12
申请号：US10381216
申请日：2001-09-21
申请人： Wolfram Drescher , Gerhard Fettweis
发明人： Wolfram Drescher , Gerhard Fettweis
IPC分类号： G06F13/36
CPC分类号： G06F13/4022
摘要： A processor bus has several data processing units, each connected to a line system which acts as a bus having bus segments connected in a separable manner through connection units. Functional units arranged on the bus carry out the information thereof. The functional units may carry out exchanges independently of each other. Conversely, functional units in different groups may carry out information exchanges simultaneously. The connection units define combinatory connections of the signal lines, with physical connections between the connection units provided by the bus segments. The connection units can carry out information exchanges with as many connected functional units as desired. The information path from a functional unit to selected functional units can be multiplexed or switched by toggling simultaneous connections to several functional units or by bridging non-participating functional units.
摘要翻译：处理器总线具有多个数据处理单元，每个数据处理单元连接到线路系统，该线路系统用作具有通过连接单元以可分离方式连接的总线段的总线。布置在总线上的功能单元执行其信息。功能单元可以彼此独立地进行交换。相反，不同组的功能单元可以同时进行信息交换。连接单元定义信号线的组合连接，以及由总线段提供的连接单元之间的物理连接。连接单元可以根据需要执行具有多个连接的功能单元的信息交换。可以通过切换与多个功能单元的同时连接或通过桥接非参与功能单元来将功能单元到所选功能单元的信息路径进行多路复用或切换。

3. 发明授权

US07685439B2 Method for effecting the controlled shutdown of data processing units 有权
标题翻译：实现数据处理单元受控停机的方法
公开(公告)号：US07685439B2
公开(公告)日：2010-03-23
申请号：US10514850
申请日：2003-05-13
申请人： Wolfram Drescher
发明人： Wolfram Drescher
IPC分类号： G06F1/00 , G06F15/76 , G06F15/80
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/329 , Y02D10/128 , Y02D10/24
摘要： Methods are provided for effecting functional control of program flow and/or data flow in digital signal processors and in processors which have closed and separated modules for effecting the program and data flow control or which operate in parallel arithmetic-logic units. The methods enhance the functionality of the signal processor to such an extent that the units of the processor, without time delays, are adapted, with regard to their energy consumption, to the latest demands of signal processing. The methods provide additional possibilities for saving energy which are enabled by algorithm-related shutdown of functional units. An external hardware-related signal input into the processor or a software-related state output from the program flow in the processor may be used to trigger an interruption in the clock pulse supply for the respective functional units for the period of time during which these functional units are not used.
摘要翻译：提供了用于实现数字信号处理器和处理器中的程序流和/或数据流的功能控制的方法，该处理器具有用于实现程序和数据流控制或者以并行运算逻辑单元工作的闭合和分离的模块。这些方法增强了信号处理器的功能，使得处理器的单元相对于其能量消耗而没有时间延迟来适应信号处理的最新需求。这些方法提供了通过功能单元的算法相关关闭来实现节能的附加可能性。输入到处理器中的外部硬件相关信号或从处理器中的程序流输出的与软件有关的状态可以被用来触发各个功能单元的时钟脉冲供给中的中断，在这段时间内这些功能不使用单位

4. 发明授权

US07577818B2 Microprocessor program addressing arrangement having multiple independent complete address generators 有权
标题翻译：具有多个独立完整地址发生器的微处理器程序寻址布置
公开(公告)号：US07577818B2
公开(公告)日：2009-08-18
申请号：US10139733
申请日：2002-05-06
申请人： Wolfram Drescher , Uwe Porst
发明人： Wolfram Drescher , Uwe Porst
IPC分类号： G06F9/30
CPC分类号： G06F9/342
摘要： An address-generating arrangement for a microprocessor has, in addition to its base address-generating unit, one or more address-generating expansion units, connected to the basic unity by an interface. The interface comprises one or more input data buses supplying data from the base unit to the expansion unit and an output data bus supplying data from the expansion unit to the basic unit under control of the microprocessor.
摘要翻译：除了基地址生成单元之外，微处理器的地址生成装置还具有通过接口连接到基本单位的一个或多个地址生成扩展单元。该接口包括从基本单元向扩展单元提供数据的一个或多个输入数据总线和在微处理器的控制下将数据从扩展单元提供给基本单元的输出数据总线。

5. 发明申请

US20080267315A1 Method and System for Transmitting Data from a Medium Access Control Device Via a Physical Layer to an Antenna 失效
标题翻译：从介质访问控制设备通过物理层向天线发送数据的方法和系统
公开(公告)号：US20080267315A1
公开(公告)日：2008-10-30
申请号：US12158308
申请日：2006-12-14
申请人： Wolfram Drescher
发明人： Wolfram Drescher
IPC分类号： H04L27/00
CPC分类号： H04J3/0685 , H04J3/0682 , H04L1/0002 , H04L27/2626
摘要： The invention relates to a method and a system for transmitting data from a medium access control device (2) via a digital interface (IF1) to a physical layer (4) and to an antenna (5), wherein the physical layer (4) comprises a base band (4) with a base band controller (7) and a data processing pipeline (3) comprising a plurality of functional blocks (FB1 . . . 13), comprising the steps of: detecting an end of a frame of payload data, which leaves the antenna (5), at a predetermined point (P1 to P3) within the data processing pipeline (3), especially at the end of the data processing pipeline (3), thereupon, starting a timer (T1) for delaying a de-assertion of an activity signal (PHY_ACTIVE) of the physical layer (4), and after expiration of the timer (T1), de-asserting the activity signal (PHY_ACTIVE).
摘要翻译：本发明涉及一种用于经由数字接口（IF 1）从媒体接入控制设备（2）向物理层（4）和天线（5）发送数据的方法和系统，其中物理层）包括具有基带控制器（7）的基带（4）和包括多个功能块（FB1.13）的数据处理流水线（3），包括以下步骤：检测帧的结束在数据处理流水线（3）内的预定点（P 1至P 3），特别是在数据处理流水线（3）的末端，离开天线（5）的有效负载数据的有效载荷数据启动计时器（T 1），用于延迟所述物理层（4）的活动信号（PHY_ACTIVE）的解除断言，并且在所述定时器（T 1）期满之后，取消所述活动信号（PHY_ACTIVE）。

6. 发明授权

US07003538B2 Process and apparatus for finite field multiplication (FFM) 有权
标题翻译：有限域乘法（FFM）的处理和装置
公开(公告)号：US07003538B2
公开(公告)日：2006-02-21
申请号：US10071708
申请日：2002-02-08
申请人： Wolfram Drescher
发明人： Wolfram Drescher
IPC分类号： G06F15/00
CPC分类号： G06F7/724
摘要： Finite field multiplication of first and second Galois elements having n bit places and belonging to a Galois field GF 2n described by an irreducible polynomial is performed by forming an intermediate result Z of intermediate sums of partial products of bit width 2n−2 in an addition part of a Galois multiplier. The intermediate result Z is processed in a reduction part of a Galois multiplier by modulo dividing by the irreducible polynomial, whereby after all XOR's are traversed a result E with n bits is computed.
摘要翻译：通过不可约多项式描述的具有n位位置并属于伽罗瓦域GF 2的第一和第二伽罗瓦元的有限域乘法通过形成位的部分乘积的中间和的中间结果Z来执行宽度2n-2在Galois乘法器的加法部分。中间结果Z通过以不可约多项式进行模除方式在伽罗瓦乘法器的缩小部分中进行处理，由此在所有XOR遍历之后，计算出n位的结果E。

7. 发明授权

US07143211B2 Memory configuration with I/O support 有权
标题翻译：具有I / O支持的内存配置
公开(公告)号：US07143211B2
公开(公告)日：2006-11-28
申请号：US10399073
申请日：2001-10-15
申请人： Wolfram Drescher , Volker Aue
发明人： Wolfram Drescher , Volker Aue
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/4217
摘要： The invention relates to a method for configuring a memory with I/O support. The aim of the invention is to guarantee the processor and I/O functional units that function in time-critical conditions the appropriate priority for data access, using simple programs. To this end, an input memory area which the I/O unit can only write into and which the processor unit can only read out of and an output memory area which the I/O unit can only read out of and which the processor unit can only write into are specified in the processor.
摘要翻译：本发明涉及一种用于配置具有I / O支持的存储器的方法。本发明的目的是使用简单的程序来保证在时间关键条件下工作的处理器和I / O功能单元适合数据访问的优先级。为此，I / O单元只能写入并且处理器单元只能读出的输入存储器区域和I / O单元只能读出的输出存储器区域以及处理器单元可以只有写入才能在处理器中指定。

8. 发明申请

US20060090060A1 Method and arrangement for bringing together data on parallel data paths 有权
标题翻译：将数据汇集在并行数据路径上的方法和装置
公开(公告)号：US20060090060A1
公开(公告)日：2006-04-27
申请号：US10505028
申请日：2003-02-12
申请人： Wolfram Drescher
发明人： Wolfram Drescher
IPC分类号： G06F15/00
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3885
摘要： A processor arrangement having a strip structure for parallel data processing is configured so that local data from the individual processing units or strips is brought together in a rapid manner. Input data, intermediate data and/or output data from various processing units are linked together in an operation which is at least partially combinatory. The data linking operation is not clock controlled. The linking of the local data from various strips in this manner reduces delays in parallel data processing in the processor arrangement. The combinatory data linking operation can provide an overall data linking outcome within an individual clock cycle.
摘要翻译：具有用于并行数据处理的带状结构的处理器装置被配置为使得来自各个处理单元或条带的本地数据以快速方式汇集在一起。来自各种处理单元的输入数据，中间数据和/或输出数据在至少部分组合的操作中被链接在一起。数据链接操作不受时钟控制。以这种方式链接来自各种条的本地数据减少了处理器布置中并行数据处理的延迟。组合数据链接操作可以在单个时钟周期内提供整体数据链接结果。

9. 发明申请

US20050216640A1 Processor bus arrangement 有权
标题翻译：处理器总线布置
公开(公告)号：US20050216640A1
公开(公告)日：2005-09-29
申请号：US10381216
申请日：2001-09-21
申请人： Wolfram Drescher , Gerhard Fettweis
发明人： Wolfram Drescher , Gerhard Fettweis
IPC分类号： G06F13/36 , G06F13/40
CPC分类号： G06F13/4022
摘要： A processor bus arrangement including several data processing units, each connected to a line system specified as a bus. The bus includes connection units and bus segments, where the bus segments are connected to the bus in a seperable manner through the connection units. This guarantees that the functional units, arranged on the bus, carry out the information thereof, by means of the bus and may carry out an exchange independently of other functional units. Furthermore, other functional units in different groups may carry out an information exchange simultaneously, by means of the bus. As the connection units perform the function of the defined combinatory connection of the signal lines, the bus segments generate the physical connections between the connection units. This ensures that the connection units carry out the information exchange with as many connected functional units as required. The information path from a functional unit can be switched by toggling to selected functional units by simultaneous connection to several functional units or by bridging non-participating functional units. One method of switching the circuitry of the connection unit is by using a multiplexer.
摘要翻译：一种处理器总线布置，包括几个数据处理单元，每个数据处理单元连接到指定为总线的线路系统。总线包括连接单元和总线段，其中总线段通过连接单元以可分离的方式连接到总线。这保证了布置在总线上的功能单元通过总线执行其信息，并且可以独立于其他功能单元执行交换。此外，不同组中的其他功能单元可以通过总线同时进行信息交换。当连接单元执行信号线的定义的组合连接的功能时，总线段产生连接单元之间的物理连接。这确保连接单元与所需的连接功能单元进行信息交换。可以通过同时连接到多个功能单元或通过桥接非参与功能单元来切换到功能单元的信息路径。切换连接单元的电路的一种方法是使用多路复用器。

10. 发明授权

US06871256B2 Method and arrangement in a stack having a memory segmented into data groups having a plurality of elements 有权
标题翻译：具有分割成具有多个元素的数据组的存储器的堆栈中的方法和布置
公开(公告)号：US06871256B2
公开(公告)日：2005-03-22
申请号：US10137781
申请日：2002-05-02
申请人： Wolfram Drescher , Uwe Porst
发明人： Wolfram Drescher , Uwe Porst
IPC分类号： G06F12/00 , G06F5/00 , G06F7/78
CPC分类号： G06F7/785 , G06F5/00
摘要： In a data memory arrangement for a microprocessor system, in which the data memory is designed as a group memory composed of element memories in which data are storable in data groups having a plurality of elements under a group address in each instance, in order to make available a stack in which the memory space can be optimally utilized without the occurrence of memory gaps, the use is proposed of at least one memory pointer that has a group address component and an element address component. The stack memory can be operated with data words whose width is smaller than the data group width, without unutilized memory areas occurring in the stack.
摘要翻译：在微处理器系统的数据存储器装置中，数据存储器被设计为由元件存储器构成的组存储器，其中数据可存储在具有在每个实例中的组地址下的多个元件的数据组中，以便使可用的堆栈，其中可以最佳地利用存储器空间而不发生存储器间隙，提出了至少一个具有组地址组件和元件地址组件的存储器指针的使用。可以使用宽度小于数据组宽度的数据字来操作堆栈存储器，而不会在堆栈中发生未使用的存储区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式