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1. 发明授权

US08350604B2 Clock receiver in semiconductor integrated circuit and method of controlling the same 有权
标题翻译：半导体集成电路中的时钟接收器及其控制方法
公开(公告)号：US08350604B2
公开(公告)日：2013-01-08
申请号：US12645630
申请日：2009-12-23
申请人： Won Joo Yun , Hyun Woo Lee , Ki-Han Kim
发明人： Won Joo Yun , Hyun Woo Lee , Ki-Han Kim
IPC分类号： H03L7/00
CPC分类号： G06F1/12
摘要： A clock receiver in a semiconductor integrated circuit includes a first clock buffer configured to buffer an external clock to generate a low frequency buffered clock in response to a first operation signal; a second clock buffer configured to buffer the external clock to generate a high frequency buffered clock in response to a second operation signal; and an internal clock generating unit configured to receive the low frequency buffered clock and the high frequency buffered clock, to control states of the first operation signal and the second operation signal and to generate an internal clock.
摘要翻译：半导体集成电路中的时钟接收器包括：第一时钟缓冲器，被配置为缓冲外部时钟以响应于第一操作信号产生低频缓冲时钟; 第二时钟缓冲器，被配置为缓冲所述外部时钟以响应于第二操作信号产生高频缓冲时钟; 以及内部时钟生成单元，被配置为接收低频缓冲时钟和高频缓冲时钟，以控制第一操作信号和第二操作信号的状态并产生内部时钟。

2. 发明授权

US08120397B2 Delay locked loop apparatus 有权
标题翻译：延迟锁定环路设备
公开(公告)号：US08120397B2
公开(公告)日：2012-02-21
申请号：US12883730
申请日：2010-09-16
申请人： Won Joo Yun , Hyun Woo Lee
发明人： Won Joo Yun , Hyun Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A delay locked loop (DLL) apparatus includes a first delay unit converting a reference clock into a rising clock. A second delay unit converts the reference clock into a falling clock, and a replica delay unit replica-delays the rising clock. A first phase detector compares the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases. A controller synchronizes the rising edge of the rising clock with the rising edge of the reference clock according to the first detection signal of the first phase detector. A second phase detector compares the phases of the synchronized rising clock and the synchronization clock to output a second detection signal corresponding to the compared phases. The DLL apparatus compensates for a skew between an external clock and data and between external and internal clocks by employing a single replica delay unit.
摘要翻译：延迟锁定环（DLL）装置包括将参考时钟转换为上升时钟的第一延迟单元。第二延迟单元将参考时钟转换为下降时钟，复制延迟单元复制延迟上升时钟。第一相位检测器比较参考时钟和延迟上升时钟的相位，以输出对应于比较相位的第一检测信号。控制器根据第一相位检测器的第一检测信号，将上升时钟的上升沿与参考时钟的上升沿同步。第二相位检测器比较同步上升时钟和同步时钟的相位，以输出对应于比较相位的第二检测信号。 DLL装置通过采用单个复制延迟单元来补偿外部时钟和数据之间以及外部和内部时钟之间的偏差。

3. 发明申请

US20100321077A1 PHASE SYNCHRONIZATION APPARATUS 有权
标题翻译：相位同步装置
公开(公告)号：US20100321077A1
公开(公告)日：2010-12-23
申请号：US12868356
申请日：2010-08-25
申请人： Hyun Woo Lee , Won Joo Yun
发明人： Hyun Woo Lee , Won Joo Yun
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0891 , H03L7/0995 , H03L7/18 , H03L2207/06
摘要： A phase synchronization apparatus includes a bias control unit configured to sequentially delay an input clock signal to generate bias control signals having multiple bits, a bias generation unit configured to generate a pull-up bias voltage having a level that corresponds to logical values of the bias control signals, and to generate a pull-down bias voltage in response to a control signal; and a voltage controlled oscillator configured to include a plurality of delay cells respectively having a pull-up terminal and a pull-down terminal to generate an output clock signal in response to the control voltage, wherein the pull-up bias voltage is supplied to the pull-up terminals of the respective delay cells and the pull-down bias voltage is supplied to the pull-down terminals of the respective delay cells.
摘要翻译：相位同步装置包括：偏置控制单元，被配置为顺序地延迟输入时钟信号以产生具有多个位的偏置控制信号;偏置生成单元，被配置为产生具有与偏置的逻辑值对应的电平的上拉偏置电压控制信号，并且响应于控制信号产生下拉偏置电压; 以及压控振荡器，被配置为包括分别具有上拉端子和下拉端子的多个延迟单元，以响应于所述控制电压而产生输出时钟信号，其中所述上拉偏置电压被提供给各个延迟单元的上拉端子和下拉偏压被提供给各个延迟单元的下拉端子。

4. 发明授权

US07750703B2 Duty cycle correcting circuit 有权
标题翻译：占空比校正电路
公开(公告)号：US07750703B2
公开(公告)日：2010-07-06
申请号：US11959368
申请日：2007-12-18
申请人： Won Joo Yun , Hyun Woo Lee , Dong Suk Shin
发明人： Won Joo Yun , Hyun Woo Lee , Dong Suk Shin
IPC分类号： H03K5/04
CPC分类号： H03K5/1565 , H03K2005/00058 , H03K2005/00208
摘要： A duty cycle correcting circuit includes a duty ratio control signal generating block that detects a duty ratio of input clock signals and generates a duty ratio control signal comprising a plurality of bits, a power supply block that supplies a voltage to output nodes, and a signal processing block that controls voltage levels of the output nodes to correspond to voltage levels of the input clock signals in response to the plurality of bits of duty ratio control signals.
摘要翻译：占空比校正电路包括占空比控制信号产生块，其检测输入时钟信号的占空比，并产生包括多个位的占空比控制信号，向输出节点提供电压的电源块和信号处理块，其响应于所述多个位占空比控制信号来控制所述输出节点的电压电平以对应于所述输入时钟信号的电压电平。

5. 发明申请

US20090003101A1 APPARATUS AND METHOD OF SETTING TEST MODE IN SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：在半导体集成电路中设置测试模式的装置和方法
公开(公告)号：US20090003101A1
公开(公告)日：2009-01-01
申请号：US12013866
申请日：2008-01-14
申请人： Won-Joo Yun , Hyun Woo Lee , Dong-Suk Shin
发明人： Won-Joo Yun , Hyun Woo Lee , Dong-Suk Shin
IPC分类号： G11C29/00
CPC分类号： G11C29/46 , G11C29/14 , G11C2029/0407 , Y10T307/747 , Y10T307/826 , Y10T307/858 , Y10T307/977
摘要： An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in response to the coding control signal.
摘要翻译：一种用于在半导体集成电路中设置测试模式的装置包括：测试模式控制块，其根据是否切断控制熔丝产生编码控制信号;以及测试模式编码块，其设置多位的默认值响应于编码控制信号的测试码。

6. 发明申请

US20080174350A1 DLL circuit and method of controlling the same 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US20080174350A1
公开(公告)日：2008-07-24
申请号：US11826401
申请日：2007-07-16
申请人： Dong Suk Shin , Hyun Woo Lee , Won Joo Yun
发明人： Dong Suk Shin , Hyun Woo Lee , Won Joo Yun
IPC分类号： H03L7/08 , H03K5/14 , H03L7/07
CPC分类号： H03K5/133 , H03K5/1565 , H03K2005/00052 , H03K2005/00065 , H03L7/0814 , H03L7/087
摘要： A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal. A duty ratio correction unit corrects a duty ratio of an internal. clock in response to the correction control signal, thereby outputting a reference clock.
摘要翻译： DLL电路包括占空比检测单元，其检测上升时钟的占空比和下降时钟的占空比，从而输出占空比检测信号。校正控制单元响应于占空比检测信号产生校正控制信号。占空比校正单元校正内部的占空比。响应于校正控制信号，从而输出参考时钟。

7. 发明授权

US08154326B2 Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit 有权
标题翻译：功率控制电路，电源控制电路的控制方法，电源控制电路的DLL电路
公开(公告)号：US08154326B2
公开(公告)日：2012-04-10
申请号：US12770702
申请日：2010-04-29
申请人： Won Joo Yun , Hyun Woo Lee , Dong Suk Shin
发明人： Won Joo Yun , Hyun Woo Lee , Dong Suk Shin
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.
摘要翻译：功率控制电路包括：检查单元，接收参考时钟并产生用于循环地激活DLL电路的反馈回路的检查信号;相位检测单元，其检测参考时钟和反馈时钟之间的相位差，并产生相位差检测信号，以及响应于锁定完成信号，检查信号和相位差检测信号产生电力切断信号的信号组合单元。

8. 发明授权

US08085072B2 Semiconductor integrated circuit having delay locked loop circuit 有权
标题翻译：具有延迟锁定环路的半导体集成电路
公开(公告)号：US08085072B2
公开(公告)日：2011-12-27
申请号：US12648380
申请日：2009-12-29
申请人： Hyun Woo Lee , Won Joo Yun
发明人： Hyun Woo Lee , Won Joo Yun
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0805 , H03L7/095
摘要： A semiconductor integrated circuit is provided. The semiconductor integrated circuit includes: a delay locked loop (DLL) output block configured to delay an input clock signal by a predetermined time in response to a plurality of delay control signals and provide a DLL clock signal; a locking control block configured to compare a phase of a reference clock signal and a phase of a feedback clock signal, and synchronize the phase of the reference clock signal and the phase of the feedback clock signal in response to the plurality of delay control signals; and a locking detection block configured to detect whether the phase of the reference clock signal and the phase of the feedback clock signal are synchronized and the DLL clock signal is locked, wherein, when the DLL clock signal is locked, the locking control block provides the reference clock signal, which is obtained by dividing the input clock signal by n (where n is a natural number equal to or greater than 2), as an internal DLL clock signal.
摘要翻译：提供半导体集成电路。半导体集成电路包括：响应于多个延迟控制信号而将输入时钟信号延迟预定时间的延迟锁定环（DLL）输出块，并提供DLL时钟信号; 锁定控制块，被配置为比较参考时钟信号的相位和反馈时钟信号的相位，并且响应于所述多个延迟控制信号使参考时钟信号的相位和反馈时钟信号的相位同步; 以及锁定检测块，被配置为检测参考时钟信号的相位和反馈时钟信号的相位是否同步，并且DLL时钟信号被锁定，其中，当DLL时钟信号被锁定时，锁定控制块提供通过将输入时钟信号除以n（其中n是等于或大于2的自然数）获得的参考时钟信号作为内部DLL时钟信号。

9. 发明申请

US20110025384A1 DEVICE FOR GENERATING CLOCK IN SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：用于在半导体集成电路中产生时钟的器件
公开(公告)号：US20110025384A1
公开(公告)日：2011-02-03
申请号：US12646608
申请日：2009-12-23
申请人： Won Joo YUN , Hyun Woo Lee , Ki Han Kim
发明人： Won Joo YUN , Hyun Woo Lee , Ki Han Kim
IPC分类号： H03L7/06 , G06F1/04
CPC分类号： G06F1/06 , H03L7/0812 , H03L7/0995 , H03L7/16
摘要： Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port.
摘要翻译：半导体集成电路的各种实施例。根据一个示例性实施例，半导体集成电路包括被配置为产生多相内部时钟的多相时钟发生器; 第一边缘组合单元，被配置为通过组合包括在所述内部时钟中的时钟的上升沿来产生具有第一频率的第一输出时钟，并将所述第一输出时钟发送到第一端口; 以及第二边缘组合单元，其被配置为通过组合包括在所述内部时钟中的时钟的上升沿来产生具有第二频率的第二输出时钟，并将所述输出时钟发送到第二端口。

10. 发明申请

US20090174447A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US20090174447A1
公开(公告)日：2009-07-09
申请号：US12176217
申请日：2008-07-18
申请人： Hyun Woo Lee , Won Joo Yun
发明人： Hyun Woo Lee , Won Joo Yun
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0802 , H03L7/087 , H03L7/095
摘要： A semiconductor integrated circuit is disclosed. The disclosed semiconductor integrated circuit of the present invention includes a DLL (Delay Locked Loop) controller that controls whether to activate a DLL at the entry of a power down mode, in response to a result of detecting whether a range of phase change of an external clock signal is within a predetermined range, and a DLL block that provides a result of comparing a reference clock signal with a feedback clock signal to the DLL controller and also provides a delay locked clock signal that is periodically updated, in response to the reference clock signal, under the control of an activated output signal from the DLL controller.
摘要翻译：公开了一种半导体集成电路。所公开的本发明的半导体集成电路包括响应于检测外部的相位变化范围的结果来控制是否在断电模式的入口处激活DLL的DLL（延迟锁定环路）时钟信号在预定范围内，以及DLL块，其将提供将参考时钟信号与反馈时钟信号进行比较的结果提供给DLL控制器，并且还响应于参考时钟提供周期性更新的延迟锁定时钟信号信号，在来自DLL控制器的激活的输出信号的控制下。

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