专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10901097B1 Method and apparatus for electronics-harmful-radiation (EHR) measurement and monitoring 有权
公开(公告)号：US10901097B1
公开(公告)日：2021-01-26
申请号：US15912088
申请日：2018-03-05
申请人： Xilinx, Inc.
发明人： James Karp , Michael J. Hart
IPC分类号： G01T1/02 , G01R31/28
摘要： An electronics-harmful-radiation (EHR) monitoring system includes an EHR measurement circuit. The EHR measurement circuit includes a first device, a single event upset (SEU) detector circuit configured to determine a first number of SEUs of the first device during a first period, and an EHR measurement generator configured to generate a first EHR value based on the first number of SEUs and the first period.

2. 发明申请

US20200091713A1 SINGLE EVENT LATCH-UP (SEL) MITIGATION DETECT AND MITIGATION 审中-公开
公开(公告)号：US20200091713A1
公开(公告)日：2020-03-19
申请号：US16136104
申请日：2018-09-19
申请人： Xilinx, Inc.
发明人： Pierre Maillard , Yanran Chen , Michael J. Hart
IPC分类号： H02H9/04 , H03K17/693
摘要： An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contract pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

3. 发明授权

US09484919B1 Selection of logic paths for redundancy 有权
标题翻译：选择冗余的逻辑路径
公开(公告)号：US09484919B1
公开(公告)日：2016-11-01
申请号：US14266547
申请日：2014-04-30
申请人： Xilinx, Inc.
发明人： Praful Jain , Pierre Maillard , James Karp , Michael J. Hart
IPC分类号： H03K19/003
CPC分类号： H03K19/00392
摘要： Approaches are disclosed for processing a circuit design to protect against single event upsets. A logic path of the circuit design is selected for redundancy based on a total of failure rates of circuit elements in the logic path being greater than a product of a target reduction in failure rate of the logic path and a failure rate of a voting circuit. The circuit design is modified to include at least three instances of the logic path coupled in parallel and a voting circuit coupled to receive output signals from the instances of the logic path. The modified circuit design is stored in a memory.
摘要翻译：公开了用于处理电路设计以防止单个事件扰乱的方法。基于逻辑路径中的电路元件的故障率的总和大于逻辑路径的故障率的目标降低与投票电路的故障率的乘积的总和，选择电路设计的逻辑路径用于冗余。电路设计被修改为包括并联耦合的逻辑路径的至少三个实例和耦合以从逻辑路径的实例接收输出信号的投票电路。修改后的电路设计存储在存储器中。

4. 发明申请

US20150069577A1 REMOVAL OF ELECTROSTATIC CHARGES FROM INTERPOSER FOR DIE ATTACHMENT 有权
标题翻译：从DIP附件的插入器中去除静电电荷
公开(公告)号：US20150069577A1
公开(公告)日：2015-03-12
申请号：US14024543
申请日：2013-09-11
申请人： Xilinx, Inc.
发明人： Michael J. Hart , James Karp
IPC分类号： H01L29/02 , H01L21/78
CPC分类号： H01L29/02 , H01L21/4846 , H01L21/78 , H01L22/32 , H01L23/3128 , H01L23/481 , H01L23/49827 , H01L23/585 , H01L23/60 , H01L24/05 , H01L24/13 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/042 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/072 , H01L25/0753 , H01L25/115 , H01L25/50 , H01L2224/16225 , H01L2224/16227 , H01L2224/752 , H01L2224/81192 , H01L2224/97 , H01L2224/81
摘要： A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network.
摘要翻译：晶片包括具有第一图案化金属层的第一插入件和具有第二图案化金属层的第二插入件。晶片包括在晶片的划线区域中的金属连接，其将第一插入器的第一图案化金属层与形成全局晶圆网络的第二插入器的第二图案化金属层电耦合。晶片还包括位于划线区域中的电耦合到全球晶片网络的探针焊盘。

5. 发明授权

US10861848B2 Single event latch-up (SEL) mitigation techniques 有权
公开(公告)号：US10861848B2
公开(公告)日：2020-12-08
申请号：US16110894
申请日：2018-08-23
申请人： Xilinx, Inc.
发明人： Michael J. Hart , James Karp , Mohammed Fakhruddin , Pierre Maillard
IPC分类号： H01L27/06 , H01L27/02 , H01L49/02 , H01L29/73 , H01L29/78
摘要： Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

6. 发明申请

US20200066837A1 SINGLE EVENT LATCH-UP (SEL) MITIGATION TECHNIQUES 审中-公开
公开(公告)号：US20200066837A1
公开(公告)日：2020-02-27
申请号：US16109273
申请日：2018-08-22
申请人： Xilinx, Inc.
发明人： James Karp , Michael J. Hart
IPC分类号： H01L29/06 , H01L27/06 , H01L27/092
摘要： Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.

7. 发明申请

US20140205934A1 SINGLE RETICLE APPROACH FOR MULTIPLE PATTERNING TECHNOLOGY 审中-公开
标题翻译：多模式技术的单一方法
公开(公告)号：US20140205934A1
公开(公告)日：2014-07-24
申请号：US13746017
申请日：2013-01-21
申请人： Xilinx, Inc.
发明人： Toshiyuki Hisamura , Michael J. Hart
IPC分类号： G03F7/20 , G03F1/00
CPC分类号： G03F7/2022 , G03F1/00 , G03F1/50 , G03F7/70466
摘要： A reticle for multiple patterning a layer of an integrated circuit die includes a first portion with a first layout pattern for multiple patterning the layer of the integrated circuit die, and a second portion with a second layout pattern for multiple patterning the layer of the integrated circuit die. The first layout pattern is different from the second layout pattern.
摘要翻译：用于多层图案化集成电路管芯层的掩模版包括具有第一布局图案的第一部分，用于对集成电路管芯的层进行多个图案化，以及具有第二布局图案的第二部分，用于对集成电路的层进行多个图案化死。第一布局模式与第二布局模式不同。

8. 发明授权

US10962588B1 Integrated circuit devices and methods of designing and producing integrated circuits 有权
公开(公告)号：US10962588B1
公开(公告)日：2021-03-30
申请号：US16041412
申请日：2018-07-20
申请人： Xilinx, Inc.
发明人： Michael J. Hart
IPC分类号： G01R31/28 , G06F30/20 , G06F30/34
摘要： A device comprising a plurality of transistors; interconnect elements coupled to the plurality of transistors is described. The interconnect elements enable the transfer of signals between the plurality of transistors. The device further includes a cooling element associated with the device, wherein the cooling element is configured to maintain a temperature of a circuit having the plurality of transistors and interconnect elements below a predetermined temperature; wherein one or more parameters of the device is optimized to operate at a temperature below the predetermined temperature. A method of implementing a circuit is also described.

9. 发明授权

US10958067B2 Single event latch-up (SEL) mitigation detect and mitigation 有权
公开(公告)号：US10958067B2
公开(公告)日：2021-03-23
申请号：US16136104
申请日：2018-09-19
申请人： Xilinx, Inc.
发明人： Pierre Maillard , Yanran Chen , Michael J. Hart
IPC分类号： H02H9/04 , H03K17/693 , H02H5/00
摘要： An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contact pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

10. 发明授权

US09628081B2 Interconnect circuits having low threshold voltage P-channel transistors for a programmable integrated circuit 有权
公开(公告)号：US09628081B2
公开(公告)日：2017-04-18
申请号：US14458017
申请日：2014-08-12
申请人： Xilinx, Inc.
发明人： Praful Jain , Michael J. Hart
IPC分类号： H03K19/0185 , H01L27/118 , H03K19/177 , H03K19/173
CPC分类号： H03K19/018571 , H01L27/11803 , H03K19/1737 , H03K19/17736 , H03K19/1776
摘要： An exemplary interconnect circuit for a programmable integrated circuit (IC) includes an input terminal coupled to receive from a node in the programmable IC, an output terminal coupled to transmit towards another node in the programmable IC, first and second control terminals coupled to receive from a memory cell of the programmable IC, and a complementary metal oxide semiconductor (CMOS) pass-gate coupled between the input terminal and the output terminal and to the first and second control terminals. The CMOS pass-gate includes a P-channel transistor configured with a low threshold voltage for a CMOS process used to fabricate the programmable IC.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式