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1. 发明授权

US09484919B1 Selection of logic paths for redundancy 有权
标题翻译：选择冗余的逻辑路径
公开(公告)号：US09484919B1
公开(公告)日：2016-11-01
申请号：US14266547
申请日：2014-04-30
申请人： Xilinx, Inc.
发明人： Praful Jain , Pierre Maillard , James Karp , Michael J. Hart
IPC分类号： H03K19/003
CPC分类号： H03K19/00392
摘要： Approaches are disclosed for processing a circuit design to protect against single event upsets. A logic path of the circuit design is selected for redundancy based on a total of failure rates of circuit elements in the logic path being greater than a product of a target reduction in failure rate of the logic path and a failure rate of a voting circuit. The circuit design is modified to include at least three instances of the logic path coupled in parallel and a voting circuit coupled to receive output signals from the instances of the logic path. The modified circuit design is stored in a memory.
摘要翻译：公开了用于处理电路设计以防止单个事件扰乱的方法。基于逻辑路径中的电路元件的故障率的总和大于逻辑路径的故障率的目标降低与投票电路的故障率的乘积的总和，选择电路设计的逻辑路径用于冗余。电路设计被修改为包括并联耦合的逻辑路径的至少三个实例和耦合以从逻辑路径的实例接收输出信号的投票电路。修改后的电路设计存储在存储器中。

2. 发明授权

US09054684B1 Single event upset enhanced architecture 有权
标题翻译：单事件加剧架构
公开(公告)号：US09054684B1
公开(公告)日：2015-06-09
申请号：US13848689
申请日：2013-03-21
申请人： Xilinx, Inc.
发明人： Santosh Kumar Sood , Praful Jain , Ramakrishna K. Tanikella
IPC分类号： H03K5/125 , G01R31/3181
CPC分类号： H03K5/125 , G01R31/31816 , G01R31/318519
摘要： A circuit block within an integrated circuit includes a multiplexor (225, 625) configured to pass either a first signal or a second signal, wherein the first signal is independent of the second signal. The circuit block further includes a first flip-flop (210, 610) configured to receive an output of the multiplexor and a second flip-flop (215, 615) configured to receive the second signal. In a first mode of operation, the multiplexor passes the first signal to the first flip-flop. Further, the first flip flop and the second flip-flop operate independently of one another. In a second mode of operation, the multiplexor passes the second signal to the first flip-flop. Further, the first flip-flop and the second flip-flop both receive the second signal.
摘要翻译：集成电路内的电路块包括经配置以通过第一信号或第二信号的多路复用器（225,625），其中第一信号独立于第二信号。电路块还包括被配置为接收多路复用器的输出的第一触发器（210,610）和被配置为接收第二信号的第二触发器（215,615）。在第一操作模式中，多路复用器将第一信号传递到第一触发器。此外，第一触发器和第二触发器彼此独立地操作。在第二操作模式中，多路复用器将第二信号传递到第一触发器。此外，第一触发器和第二触发器都接收第二信号。

3. 发明授权

US09183338B1 Single-event upset mitigation in circuit design for programmable integrated circuits 有权
标题翻译：用于可编程集成电路的电路设计中的单事件缓解
公开(公告)号：US09183338B1
公开(公告)日：2015-11-10
申请号：US14487286
申请日：2014-09-16
申请人： Xilinx, Inc.
发明人： Praful Jain , Pierre Maillard
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/505
摘要： In an example, a method of implementing a circuit design for a programmable integrated circuit (IC) begins by identifying combinatorial logic functions of the circuit design. The method maps, according to a first constraint, a first threshold percentage of the combinatorial logic functions onto a first type of lookup tables (LUTs) of the programmable IC in favor of second type of LUTs of the programmable IC, the second type of LUTs being more susceptible to single event upsets than the first type of LUTs. The method generates a first physical implementation of the circuit design for the programmable IC based on the mapping.
摘要翻译：在一个示例中，实现可编程集成电路（IC）的电路设计的方法开始于识别电路设计的组合逻辑功能。该方法根据第一约束将组合逻辑功能的第一阈值百分比映射到可编程IC的第一类型的查找表（LUT），有利于可编程IC的第二类型的LUT，第二类型的LUT 比第一类型的LUT更容易受到单事件的影响。该方法基于映射生成可编程IC的电路设计的第一个物理实现。

4. 发明申请

US20140145293A1 INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY 有权
标题翻译：具有改善辐射免疫力的集成电路
公开(公告)号：US20140145293A1
公开(公告)日：2014-05-29
申请号：US13686553
申请日：2012-11-27
申请人： Xilinx, Inc.
发明人： Praful Jain , James Karp , Michael J. Hart
IPC分类号： H01L23/552 , H01L21/02
CPC分类号： H01L23/552 , G11C11/4125 , H01L21/02697 , H01L27/0207 , H01L27/1104 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors.
摘要翻译：描述了具有改善的辐射抗扰性的集成电路。集成电路包括基板; 在衬底上形成的P阱，并具有存储单元的N型晶体管; 和形成在衬底上并具有存储单元的P型晶体管的N阱; 其中所述N阱具有用于容纳所述P型晶体管的最小尺寸。

5. 发明授权

US11041211B2 Power distribution for active-on-active die stack with reduced resistance 有权
公开(公告)号：US11041211B2
公开(公告)日：2021-06-22
申请号：US15902703
申请日：2018-02-22
申请人： Xilinx, Inc.
发明人： Praful Jain
IPC分类号： H01L23/522 , C12Q1/6886 , G01N33/574 , C07K16/32
摘要： Active-on-active microelectronic devices are described. For example, a first die is on a second die with a bottom surface of a first substrate facing a top surface of a second substrate, respectively, to provide a die stack. The first and second dies each have metal layers in ILD layers to provide a first stack structure and a second stack structure, respectively. The first stack structure is interconnected to an upper end of a TSV of the first die. A metal layer of the second stack structure near a bottom surface of the first substrate is interconnected to a lower end of the TSV. A power distribution network layer of the second stack structure is located between lower and upper layers of the metal layers thereof. A transistor located at least in part in the second substrate is interconnected to the power distribution network layer to receive supply voltage or ground.

6. 发明申请

US20190259702A1 POWER DISTRIBUTION FOR ACTIVE-ON-ACTIVE DIE STACK WITH REDUCED RESISTANCE 审中-公开
公开(公告)号：US20190259702A1
公开(公告)日：2019-08-22
申请号：US15902703
申请日：2018-02-22
申请人： Xilinx, Inc.
发明人： Praful Jain
IPC分类号： H01L23/522 , H01L25/00 , H01L23/48 , H01L25/065
摘要： Active-on-active microelectronic devices are described. For example, a first die is on a second die with a bottom surface of a first substrate facing a top surface of a second substrate, respectively, to provide a die stack. The first and second dies each have metal layers in ILD layers to provide a first stack structure and a second stack structure, respectively. The first stack structure is interconnected to an upper end of a TSV of the first die. A metal layer of the second stack structure near a bottom surface of the first substrate is interconnected to a lower end of the TSV. A power distribution network layer of the second stack structure is located between lower and upper layers of the metal layers thereof. A transistor located at least in part in the second substrate is interconnected to the power distribution network layer to receive supply voltage or ground.

7. 发明授权

US09483599B1 Circuit design-specific failure in time rate for single event upsets 有权
标题翻译：电路设计特定的单事件故障时间速率故障
公开(公告)号：US09483599B1
公开(公告)日：2016-11-01
申请号：US14494361
申请日：2014-09-23
申请人： Xilinx, Inc.
发明人： Praful Jain , James Karp
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5022 , G06F17/5054 , G06F17/5081
摘要： Determining a circuit design-specific, failures in time rate for single event upsets for an integrated circuit (IC) includes determining, using a processor, a number of critical interconnect multiplexer bits for a circuit design for a target IC and determining a number of critical look-up table bits for the circuit design. Using the processor, a device vulnerability factor is estimated for the circuit design for the target IC using the number of critical interconnect multiplexer bits and the number of critical look-up table bits. The estimated device vulnerability factor can be stored, e.g., for subsequent comparison with other circuit designs.
摘要翻译：确定电路设计特定的集成电路（IC）的单事件故障的时间速率失败包括使用处理器确定用于目标IC的电路设计的多个关键互连多路复用器位，并确定关键的数量查找表位用于电路设计。使用处理器，使用关键互连复用器位数和关键查找表位数来估计目标IC的电路设计的设备漏洞因素。可以存储估计的设备脆弱性因子，例如用于随后与其他电路设计的比较。

8. 发明授权

US10908598B1 Integrated circuits designed for multiple sets of criteria 有权
公开(公告)号：US10908598B1
公开(公告)日：2021-02-02
申请号：US16426945
申请日：2019-05-30
申请人： XILINX, INC.
发明人： Praful Jain
IPC分类号： G05B19/418 , G06F30/30
摘要： Examples described herein provide a method for designing an integrated circuit (IC) for meeting different sets of criteria. In an example, different sets of criteria are identified for an IC design. The IC design is designed to meet the different sets of criteria based on expected manufacturing variation. The IC design is caused to be manufactured as IC products. At least some of the IC products are caused to be tested. The IC products are characterized as meeting respective ones of the different sets of criteria based on testing the at least some of the IC products.

9. 发明授权

US09628081B2 Interconnect circuits having low threshold voltage P-channel transistors for a programmable integrated circuit 有权
公开(公告)号：US09628081B2
公开(公告)日：2017-04-18
申请号：US14458017
申请日：2014-08-12
申请人： Xilinx, Inc.
发明人： Praful Jain , Michael J. Hart
IPC分类号： H03K19/0185 , H01L27/118 , H03K19/177 , H03K19/173
CPC分类号： H03K19/018571 , H01L27/11803 , H03K19/1737 , H03K19/17736 , H03K19/1776
摘要： An exemplary interconnect circuit for a programmable integrated circuit (IC) includes an input terminal coupled to receive from a node in the programmable IC, an output terminal coupled to transmit towards another node in the programmable IC, first and second control terminals coupled to receive from a memory cell of the programmable IC, and a complementary metal oxide semiconductor (CMOS) pass-gate coupled between the input terminal and the output terminal and to the first and second control terminals. The CMOS pass-gate includes a P-channel transistor configured with a low threshold voltage for a CMOS process used to fabricate the programmable IC.

10. 发明授权

US09281807B1 Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit 有权
标题翻译：主从触发器和在集成电路中实现主从触发器的方法
公开(公告)号：US09281807B1
公开(公告)日：2016-03-08
申请号：US14299196
申请日：2014-06-09
申请人： Xilinx, Inc.
发明人： Pierre Maillard , Praful Jain , Michael J. Hart , Sundeep Ram Gopal Agarwal , Austin H. Lesea , Jun Liu
IPC分类号： H03K3/023 , H03K3/037
CPC分类号： H03K3/35625 , H03K3/356156
摘要： A master-slave flip-flop implemented in an integrated circuit comprises a master latch coupled to receive data at an input; and a slave latch coupled to an output of the master latch, wherein the slave latch comprises an SEU-enhanced latch, and the master latch is not enhanced for SEU protection. A method of implementing a master-slave flip-flop in an integrated circuit is also described.
摘要翻译：在集成电路中实现的主从触发器包括耦合以在输入端接收数据的主锁存器; 以及耦合到主锁存器的输出的从锁存器，其中从锁存器包括SEU增强锁存器，并且主锁存器不增强用于SEU保护。还描述了在集成电路中实现主从触发器的方法。

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