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1. 发明授权

US10033388B1 Circuit for and method of enabling the selection of a circuit 有权
公开(公告)号：US10033388B1
公开(公告)日：2018-07-24
申请号：US15465402
申请日：2017-03-21
申请人： Xilinx, Inc.
发明人： Mini Rawat , Pierre Maillard , Michael J. Hart
IPC分类号： H03K19/177 , H03K19/00
摘要： An integrated circuit enables the selection of a circuit. According to one implementation, a plurality of redundant circuits provide a predetermined function and a voltage sensor may be coupled to receive a reference voltage. A selection circuit may be coupled to the voltage sensor and the reference voltage, wherein the selection circuit selects one of the plurality of redundant circuits to be implemented in the integrated circuit based upon a detected voltage of the reference voltage of the reference voltage.

2. 发明授权

US09183338B1 Single-event upset mitigation in circuit design for programmable integrated circuits 有权
标题翻译：用于可编程集成电路的电路设计中的单事件缓解
公开(公告)号：US09183338B1
公开(公告)日：2015-11-10
申请号：US14487286
申请日：2014-09-16
申请人： Xilinx, Inc.
发明人： Praful Jain , Pierre Maillard
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/505
摘要： In an example, a method of implementing a circuit design for a programmable integrated circuit (IC) begins by identifying combinatorial logic functions of the circuit design. The method maps, according to a first constraint, a first threshold percentage of the combinatorial logic functions onto a first type of lookup tables (LUTs) of the programmable IC in favor of second type of LUTs of the programmable IC, the second type of LUTs being more susceptible to single event upsets than the first type of LUTs. The method generates a first physical implementation of the circuit design for the programmable IC based on the mapping.
摘要翻译：在一个示例中，实现可编程集成电路（IC）的电路设计的方法开始于识别电路设计的组合逻辑功能。该方法根据第一约束将组合逻辑功能的第一阈值百分比映射到可编程IC的第一类型的查找表（LUT），有利于可编程IC的第二类型的LUT，第二类型的LUT 比第一类型的LUT更容易受到单事件的影响。该方法基于映射生成可编程IC的电路设计的第一个物理实现。

3. 发明授权

US10861848B2 Single event latch-up (SEL) mitigation techniques 有权
公开(公告)号：US10861848B2
公开(公告)日：2020-12-08
申请号：US16110894
申请日：2018-08-23
申请人： Xilinx, Inc.
发明人： Michael J. Hart , James Karp , Mohammed Fakhruddin , Pierre Maillard
IPC分类号： H01L27/06 , H01L27/02 , H01L49/02 , H01L29/73 , H01L29/78
摘要： Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

4. 发明授权

US10366999B2 Single event upset (SEU) mitigation for FinFET technology using fin topology 有权
公开(公告)号：US10366999B2
公开(公告)日：2019-07-30
申请号：US15087947
申请日：2016-03-31
申请人： Xilinx, Inc.
发明人： Pierre Maillard
IPC分类号： H01L27/11 , H01L29/08 , H01L29/78 , H01L27/088 , H01L27/092
摘要： Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (HTOT) and a width W. The height (HTOT) is greater than an optimal height (HOPT), wherein the height HOPT is a height that would optimize speed of a FinFET transistor having the width W.

5. 发明授权

US10958067B2 Single event latch-up (SEL) mitigation detect and mitigation 有权
公开(公告)号：US10958067B2
公开(公告)日：2021-03-23
申请号：US16136104
申请日：2018-09-19
申请人： Xilinx, Inc.
发明人： Pierre Maillard , Yanran Chen , Michael J. Hart
IPC分类号： H02H9/04 , H03K17/693 , H02H5/00
摘要： An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contact pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

6. 发明申请

US20170287919A1 SINGLE EVENT UPSET (SEU) MITIGATION FOR FINFET TECHNOLOGY USING FIN TOPOLOGY 审中-公开
公开(公告)号：US20170287919A1
公开(公告)日：2017-10-05
申请号：US15087947
申请日：2016-03-31
申请人： Xilinx, Inc.
发明人： Pierre Maillard
IPC分类号： H01L27/11 , H01L29/08 , H01L29/78
CPC分类号： H01L27/1116 , H01L27/0886 , H01L27/0924 , H01L27/1104 , H01L29/0847 , H01L29/785 , H01L29/7851
摘要： Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (HTOT) and a width W. The height (HTOT) is greater than an optimal height (HOPT), wherein the height HOPT is a height that would optimize speed of a FinFET transistor having the width W.

7. 发明授权

US09281807B1 Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit 有权
标题翻译：主从触发器和在集成电路中实现主从触发器的方法
公开(公告)号：US09281807B1
公开(公告)日：2016-03-08
申请号：US14299196
申请日：2014-06-09
申请人： Xilinx, Inc.
发明人： Pierre Maillard , Praful Jain , Michael J. Hart , Sundeep Ram Gopal Agarwal , Austin H. Lesea , Jun Liu
IPC分类号： H03K3/023 , H03K3/037
CPC分类号： H03K3/35625 , H03K3/356156
摘要： A master-slave flip-flop implemented in an integrated circuit comprises a master latch coupled to receive data at an input; and a slave latch coupled to an output of the master latch, wherein the slave latch comprises an SEU-enhanced latch, and the master latch is not enhanced for SEU protection. A method of implementing a master-slave flip-flop in an integrated circuit is also described.
摘要翻译：在集成电路中实现的主从触发器包括耦合以在输入端接收数据的主锁存器; 以及耦合到主锁存器的输出的从锁存器，其中从锁存器包括SEU增强锁存器，并且主锁存器不增强用于SEU保护。还描述了在集成电路中实现主从触发器的方法。

8. 发明申请

US20200091713A1 SINGLE EVENT LATCH-UP (SEL) MITIGATION DETECT AND MITIGATION 审中-公开
公开(公告)号：US20200091713A1
公开(公告)日：2020-03-19
申请号：US16136104
申请日：2018-09-19
申请人： Xilinx, Inc.
发明人： Pierre Maillard , Yanran Chen , Michael J. Hart
IPC分类号： H02H9/04 , H03K17/693
摘要： An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contract pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

9. 发明授权

US09484919B1 Selection of logic paths for redundancy 有权
标题翻译：选择冗余的逻辑路径
公开(公告)号：US09484919B1
公开(公告)日：2016-11-01
申请号：US14266547
申请日：2014-04-30
申请人： Xilinx, Inc.
发明人： Praful Jain , Pierre Maillard , James Karp , Michael J. Hart
IPC分类号： H03K19/003
CPC分类号： H03K19/00392
摘要： Approaches are disclosed for processing a circuit design to protect against single event upsets. A logic path of the circuit design is selected for redundancy based on a total of failure rates of circuit elements in the logic path being greater than a product of a target reduction in failure rate of the logic path and a failure rate of a voting circuit. The circuit design is modified to include at least three instances of the logic path coupled in parallel and a voting circuit coupled to receive output signals from the instances of the logic path. The modified circuit design is stored in a memory.
摘要翻译：公开了用于处理电路设计以防止单个事件扰乱的方法。基于逻辑路径中的电路元件的故障率的总和大于逻辑路径的故障率的目标降低与投票电路的故障率的乘积的总和，选择电路设计的逻辑路径用于冗余。电路设计被修改为包括并联耦合的逻辑路径的至少三个实例和耦合以从逻辑路径的实例接收输出信号的投票电路。修改后的电路设计存储在存储器中。

10. 发明授权

US09236354B2 Integrated circuit package with thermal neutron shielding 有权
标题翻译：具有热中子屏蔽的集成电路封装
公开(公告)号：US09236354B2
公开(公告)日：2016-01-12
申请号：US14257853
申请日：2014-04-21
申请人： Xilinx, Inc.
发明人： Pierre Maillard , Jeffrey Barton , Austin H. Lesea
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , H01L21/563 , H01L23/3128 , H01L25/0655 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/16152 , H01L2924/00
摘要： A semiconductor package with thermal neutron shielding is disclosed. The semiconductor package includes a substrate and an integrated circuit die disposed on the substrate. The semiconductor package also has a thermal neutron shield including a shielding material. The shielding material includes boron-10 and is configured to inhibit a portion of thermal neutrons that encounter the thermal neutron shield from passing through the thermal neutron shield.
摘要翻译：公开了一种具有热中子屏蔽的半导体封装。半导体封装包括衬底和设置在衬底上的集成电路管芯。半导体封装还具有包括屏蔽材料的热中子屏蔽。屏蔽材料包括硼-10并且被配置为抑制遇到热中子屏蔽的热中子的一部分通过热中子屏蔽。

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