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1. 发明申请

US20070070707A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070070707A1
公开(公告)日：2007-03-29
申请号：US11526057
申请日：2006-09-25
申请人： Yasue Yamamoto , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki
发明人： Yasue Yamamoto , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki
IPC分类号： G11C11/34
CPC分类号： G11C16/0416 , G11C2216/10 , H01L27/105 , H01L27/11521 , H01L27/11558
摘要： A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.
摘要翻译：用于通过在浮动栅极中累积电荷来存储数据的非易失性半导体存储器件包括共享浮置栅极的多个MOS晶体管。在器件中，在写入期间使用PMOS耦合并且在擦除期间使用n型耗尽MOS（DMOS）耦合。与传统的三晶体管非易失性存储元件相比，通过PMOS将沟道反转电容耦合用于n型DMOS的耗尽电容的写入和耦合用于擦除，从而增加擦除速度而不增加面积。

2. 发明申请

US20070069803A1 Charge-pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US20070069803A1
公开(公告)日：2007-03-29
申请号：US11526060
申请日：2006-09-25
申请人： Yasue Yamamoto , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki
发明人： Yasue Yamamoto , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A circuit includes a plurality of stages each including a MOS transistor and a capacitor of which one end is connected to one of a drain and a source of the MOS transistor. The plurality of stages are connected with each other by cascade connection of the MOS transistors. A gate of the MOS transistor is connected electrically to one of the drain and the source thereof in each stage, and a substrate for at least one pair of adjacent MOS transistors are connected electrically to one of the drain and the source of one of the pair. The back bias effect is suppressed, and the layout area is reduced. Further, a plurality of booster capacitors connected in series are provided in succeeding stages, thereby suppressing degradation of breakdown voltage of each capacitor.
摘要翻译：电路包括多个级，每个级包括MOS晶体管和电容器，其一端连接到MOS晶体管的漏极和源极之一。多个级通过MOS晶体管的级联连接而相互连接。 MOS晶体管的栅极在每个级中电连接到漏极和源极之一，并且用于至少一对相邻MOS晶体管的衬底电连接到该对之一的漏极和源极之一。背偏置效果被抑制，布局面积减小。此外，在后续阶段提供串联连接的多个升压电容器，从而抑制每个电容器的击穿电压的劣化。

3. 发明授权

US07602231B2 Charge-pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US07602231B2
公开(公告)日：2009-10-13
申请号：US11526060
申请日：2006-09-25
申请人： Yasue Yamamoto , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki
发明人： Yasue Yamamoto , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki
IPC分类号： G05F3/24 , H02M3/16 , H01L27/04
CPC分类号： H02M3/07
摘要： A circuit includes a plurality of stages each including a MOS transistor and a capacitor of which one end is connected to one of a drain and a source of the MOS transistor. The plurality of stages are connected with each other by cascade connection of the MOS transistors. A gate of the MOS transistor is connected electrically to one of the drain and the source thereof in each stage, and a substrate for at least one pair of adjacent MOS transistors are connected electrically to one of the drain and the source of one of the pair. The back bias effect is suppressed, and the layout area is reduced. Further, a plurality of booster capacitors connected in series are provided in succeeding stages, thereby suppressing degradation of breakdown voltage of each capacitor.
摘要翻译：电路包括多个级，每个级包括MOS晶体管和电容器，其一端连接到MOS晶体管的漏极和源极之一。多个级通过MOS晶体管的级联连接而相互连接。 MOS晶体管的栅极在每个级中电连接到漏极和源极之一，并且用于至少一对相邻MOS晶体管的衬底电连接到该对之一的漏极和源极之一。背偏置效果被抑制，布局面积减小。此外，在后续阶段提供串联连接的多个升压电容器，从而抑制每个电容器的击穿电压的劣化。

4. 发明申请

US20090189226A1 ELECTRICAL FUSE CIRCUIT 审中-公开
标题翻译：电气保险丝电路
公开(公告)号：US20090189226A1
公开(公告)日：2009-07-30
申请号：US12247647
申请日：2008-10-08
申请人： Yasue YAMAMOTO , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki
发明人： Yasue YAMAMOTO , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki
IPC分类号： H01L29/00
CPC分类号： G11C17/16 , G11C17/18
摘要： An electrical fuse circuit includes, in addition to an independent power supply switch circuit, a plurality of fuse bit cells, each including a fuse element one end of which is connected to an output of the power supply switch circuit, and a first MOS transistor connected to the other end of the fuse element, wherein a diode is connected between the ground potential and the power supply switch circuit as an ESD countermeasure. The gate oxide film thickness of transistors of the fuse bit cells is equal to that of a low-voltage logic-type transistor, not that of a high-voltage I/O-type transistor.
摘要翻译：除了独立的电源开关电路之外，电熔丝电路还包括多个熔丝位单元，每个熔丝位单元包括一个熔丝元件，其一端连接到电源开关电路的输出端，第一MOS晶体管连接连接到熔丝元件的另一端，其中二极管作为ESD对策连接在地电位和电源开关电路之间。熔丝位单元的晶体管的栅极氧化膜厚度等于低压逻辑型晶体管的栅极氧化膜厚度，而不是高电压I / O型晶体管的晶体管的栅极氧化膜厚度。

5. 发明授权

US07397720B2 Semiconductor storage device including electrical fuse module 有权
标题翻译：半导体存储装置包括电熔丝模块
公开(公告)号：US07397720B2
公开(公告)日：2008-07-08
申请号：US11501039
申请日：2006-08-09
申请人： Shinichi Sumi , Hirohito Kikukawa , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Ryuji Nishihara , Yasue Yamamoto
发明人： Shinichi Sumi , Hirohito Kikukawa , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Ryuji Nishihara , Yasue Yamamoto
IPC分类号： G11C17/18 , G11C17/00
CPC分类号： G11C17/16 , G11C17/165 , G11C29/027 , G11C29/785 , G11C2229/763
摘要： Electrical fuse blocks (100) of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (101). The electrical fuse block (100) includes a program shift register block (103) made up of shift registers (107) which are disposed for the respective electrical fuse cores (101), sequentially transmit program enable signal FPGI, and output the program enable signal FPGI to the NMOS transistors (105) of the electrical fuse cores (101). When performing programming according to programming decision signal PBn, the program shift register block (103) transmits the program enable signal FPGI. When not performing programming, the program shift register block (103) skips the program enable signal FPGI.
摘要翻译：提供多级的电熔丝块（100），每个级包括多个电熔丝芯（101）。电熔丝块（100）包括由移位寄存器（107）构成的程序移位寄存器块（103），它们被设置用于相应的电熔丝芯（101），顺序发送编程使能信号FPGI，并输出编程使能信号 FPGI连接到电熔丝芯（101）的NMOS晶体管（105）。当根据编程判定信号PBn执行编程时，程序移位寄存器块（103）发送程序使能信号FPGI。当不执行编程时，程序移位寄存器块（103）跳过编程使能信号FPGI。

6. 发明申请

US20080150613A1 Electrical fuse circuit 有权
标题翻译：电熔丝电路
公开(公告)号：US20080150613A1
公开(公告)日：2008-06-26
申请号：US11976672
申请日：2007-10-26
申请人： Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Shinichi Sumi , Yasue Yamamoto
发明人： Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Shinichi Sumi , Yasue Yamamoto
IPC分类号： H01H37/76
CPC分类号： G11C17/18 , H01L24/05 , H01L27/0629 , H01L2224/48091 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A gate of a MOS transistor connected to a fuse device in series is controlled by an AND circuit connected to the same power source as the fuse device is connected, thereby pulling down one input of the AND circuit to a ground. Thus, misprogramming of the fuse device when an LSI power source is turned ON/OFF can be prevented.
摘要翻译：连接到串联熔丝器件的MOS晶体管的栅极由连接到与熔丝器件连接的相同电源的AND电路控制，从而将AND电路的一个输入端拉到地。因此，可以防止当LSI电源接通/断开时熔丝装置的错编程。

7. 发明申请

US20070097573A1 System LSI 有权
标题翻译：系统LSI
公开(公告)号：US20070097573A1
公开(公告)日：2007-05-03
申请号：US11526816
申请日：2006-09-26
申请人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
发明人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
IPC分类号： H02H3/20
CPC分类号： G11C5/063 , G11C5/14 , G11C17/165 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.
摘要翻译：系统LSI包括输入/输出部分和逻辑电路部分。输入/输出部分包括具有高于用于逻辑电路部分的电源的电源电压的I / O电源单元和设置有I / O电源线的多个I / O单元，用于提供来自I / O电源单元的源电源。逻辑电路部分包括使用I / O电源单元作为电源的I / O功耗电路。 I / O消耗电路连接到从多个I / O单元中的至少一个中的I / O电源线引出的线。

8. 发明授权

US07884642B2 System LSI 有权
标题翻译：系统LSI
公开(公告)号：US07884642B2
公开(公告)日：2011-02-08
申请号：US12722317
申请日：2010-03-11
申请人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
发明人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
IPC分类号： H03K19/173
CPC分类号： G11C5/063 , G11C5/14 , G11C17/165 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.
摘要翻译：系统LSI包括输入/输出部分和逻辑电路部分。输入/输出部分包括具有高于用于逻辑电路部分的电源的电源电压的I / O电源单元和设置有I / O电源线的多个I / O单元，用于提供来自I / O电源单元的源电源。逻辑电路部分包括使用I / O电源单元作为电源的I / O功耗电路。 I / O消耗电路连接到从多个I / O单元中的至少一个中的I / O电源线引出的线。

9. 发明授权

US07764108B2 Electrical fuse circuit 有权
标题翻译：电熔丝电路
公开(公告)号：US07764108B2
公开(公告)日：2010-07-27
申请号：US11976672
申请日：2007-10-26
申请人： Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Shinichi Sumi , Yasue Yamamoto
发明人： Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Shinichi Sumi , Yasue Yamamoto
IPC分类号： H01H37/76
CPC分类号： G11C17/18 , H01L24/05 , H01L27/0629 , H01L2224/48091 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A gate of a MOS transistor connected to a fuse device in series is controlled by an AND circuit connected to the same power source as the fuse device is connected, thereby pulling down one input of the AND circuit to a ground. Thus, misprogramming of the fuse device when an LSI power source is turned ON/OFF can be prevented.
摘要翻译：连接到串联熔丝器件的MOS晶体管的栅极由连接到与熔丝器件连接的相同电源的AND电路控制，从而将AND电路的一个输入端拉到地。因此，可以防止当LSI电源接通/断开时熔丝装置的错编程。

10. 发明授权

US07755941B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07755941B2
公开(公告)日：2010-07-13
申请号：US11971334
申请日：2008-01-09
申请人： Yasue Yamamoto , Masanori Shirahama , Yasuhiro Agata , Toshiaki Kawasaki
发明人： Yasue Yamamoto , Masanori Shirahama , Yasuhiro Agata , Toshiaki Kawasaki
IPC分类号： G11C16/04
CPC分类号： G11C16/0441 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.
摘要翻译：在通过在浮动栅极中积累电荷来存储数据的非易失性半导体存储器件中，每个包括作为读取器件的第一MOS晶体管的存储器单元，由作为电容耦合器件的第一电容器构成的位单元和第二电容器擦除装置，以及包括第二MOS晶体管和第三MOS晶体管的解码装置。这实现了能够排列成阵列的逐位选择性擦除的非易失性存储器，从而显着地减小了核心区域。

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