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1. 发明授权

US07772814B2 Step-down circuit 有权
标题翻译：降压电路
公开(公告)号：US07772814B2
公开(公告)日：2010-08-10
申请号：US11971579
申请日：2008-01-09
申请人： Yasuhiro Suematsu , Katsumi Abe
发明人： Yasuhiro Suematsu , Katsumi Abe
IPC分类号： G05F1/565 , G05F1/40
CPC分类号： G05F1/575
摘要： A step-down circuit generates a second power supply lower than a first power supply. The step-down circuit includes an output terminal connected to a load circuit, an output transistor connected between the first power supply and the output terminal, and having a gate terminal connected to a first node, a monitor transistor connected between the first power supply and a second node, and having a gate terminal connected to the first node, and a feedback circuit which sets a gate voltage of the output transistor in accordance with a difference between a voltage obtained by dividing a voltage of the second node and a reference voltage. A size of the monitor transistor is changed in accordance with an operation mode of the load circuit.
摘要翻译：降压电路产生低于第一电源的第二电源。降压电路包括连接到负载电路的输出端子，连接在第一电源和输出端子之间的输出晶体管，并且具有连接到第一节点的栅极端子，连接在第一电源和第二节点，并且具有连接到第一节点的栅极端子;以及反馈电路，其根据通过分割第二节点的电压而获得的电压与参考电压之间的差设置输出晶体管的栅极电压。监视晶体管的尺寸根据负载电路的工作模式而改变。

2. 发明授权

US06999356B2 Semiconductor device capable of readjusting a reference potential during the reliabilty test 失效
标题翻译：在可靠性测试期间能够重新调整参考电位的半导体器件
公开(公告)号：US06999356B2
公开(公告)日：2006-02-14
申请号：US10941999
申请日：2004-09-16
申请人： Eiji Kozuka , Yasuhiro Suematsu , Kazuaki Kawaguchi , Mikio Miyata
发明人： Eiji Kozuka , Yasuhiro Suematsu , Kazuaki Kawaguchi , Mikio Miyata
IPC分类号： G11C7/14
CPC分类号： G11C29/021 , G11C29/006 , G11C29/02 , G11C29/12005
摘要： A semiconductor device that generates a desired internal power supply by using, as a reference potential, a potential obtained by adjusting a preset standard potential, the semiconductor device comprises; a reference potential selection circuit selecting the reference potential on the basis of digital data from among a plurality of potentials of different levels which are obtained by dividing a power supply voltage, and outputting the reference potential instead of the standard potential; a first decision circuit deciding bits of the digital data; a second decision circuit deciding the bits of the digital data, separately from the first decision circuit; and a data transfer circuit transferring to the reference potential selection circuit the digital data which is decided by either one of the first and second decision circuits.
摘要翻译：一种半导体器件，其通过使用通过调整预设标准电位而获得的电位作为参考电位来产生期望的内部电源，所述半导体器件包括：参考电位选择电路，其基于通过划分电源电压获得的不同电平的多个电位中的数字数据，并输出参考电位而不是标准电位来选择参考电位; 确定所述数字数据的位的第一判定电路; 第二判定电路，与第一判定电路分开地决定数字数据的位; 以及数据传送电路，将由第一和第二判定电路中的任一个决定的数字数据传送到参考电位选择电路。

3. 发明申请

US20050116696A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20050116696A1
公开(公告)日：2005-06-02
申请号：US10962617
申请日：2004-10-13
申请人： Yasuhiro Suematsu
发明人： Yasuhiro Suematsu
IPC分类号： G11C11/407 , G05F1/40 , G11C5/14
CPC分类号： G11C5/14
摘要： A semiconductor integrated circuit device according to a first aspect of the present invention includes: a first internal power source voltage generating circuit which includes a voltage boosting circuit and a level determining circuit, and outputs a first internal power source voltage, the voltage boosting circuit boosting a voltage based upon a voltage boosting start instruction signal after putting on a power supply, and the level determining circuit which generates a first control signal when an output voltage from the voltage boosting circuit reaches a first level and generates a second control signal for stopping the voltage boosting of the voltage boosting circuit when the output voltage from the voltage boosting circuit reaches a second level higher than the first level; a first control circuit which generates a first action start instruction signal based upon the voltage boosting start instruction signal and the first control signal; and a second internal power source voltage generating circuit which generates a second internal power source voltage based upon the first action start instruction signal.
摘要翻译：根据本发明的第一方面的半导体集成电路器件包括：第一内部电源电压产生电路，其包括升压电路和电平确定电路，并且输出第一内部电源电压，所述升压电路升压在施加电源之后基于升压开始指令信号的电压;以及当来自升压电路的输出电压达到第一电平时产生第一控制信号的电平确定电路，并且产生用于停止电压的第二控制信号当升压电路的输出电压达到高于第一电平的第二电平时升压电路的升压; 第一控制电路，其基于所述升压开始指示信号和所述第一控制信号生成第一动作开始指示信号; 以及第二内部电源电压产生电路，其基于第一动作开始指令信号产生第二内部电源电压。

4. 发明授权

US08405432B2 Output buffer circuit, input buffer circuit, and input/output buffer circuit 有权
标题翻译：输出缓冲电路，输入缓冲电路，输入/输出缓冲电路
公开(公告)号：US08405432B2
公开(公告)日：2013-03-26
申请号：US12963114
申请日：2010-12-08
申请人： Masaru Koyanagi , Yasufumi Kajiyama , Ryo Fukuda , Fumiyoshi Matsuoka , Yasuhiro Suematsu
发明人： Masaru Koyanagi , Yasufumi Kajiyama , Ryo Fukuda , Fumiyoshi Matsuoka , Yasuhiro Suematsu
IPC分类号： H03K3/01
CPC分类号： H03K19/00384 , H03K19/01721
摘要： An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.
摘要翻译：根据实施例的输出缓冲器电路包括多个缓冲电路，每个缓冲电路包括一个晶体管，用于响应于输入信号的变化而改变输出端的输出信号，该输出缓冲电路被配置以使得能够选择性地驱动多个缓冲电路。多个缓冲电路中的每一个包括多个输出晶体管，其具有在提供一定固定电压的固定电压端子和输出端子之间彼此并联形成的各自的电流路径，并且根据控制信号由外部提供。包含在多个缓冲电路的每一个中的多个输出晶体管形成为具有一定的尺寸比。

5. 发明授权

US07576523B2 Power supply circuit and semiconductor memory 有权
标题翻译：电源电路和半导体存储器
公开(公告)号：US07576523B2
公开(公告)日：2009-08-18
申请号：US12125589
申请日：2008-05-22
申请人： Mikio Ogawa , Yasuhiro Suematsu
发明人： Mikio Ogawa , Yasuhiro Suematsu
IPC分类号： G05F1/40 , H02M3/18 , G11C7/00
CPC分类号： H02M3/073 , G11C5/143 , G11C5/145 , G11C16/30
摘要： A power supply circuit that outputs a set voltage from an output terminal, has a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first detecting signal when the voltage outputted from the boosting circuit is not lower than a first detection voltage set lower than the set voltage, and outputs a second detecting signal when the voltage outputted from the boosting circuit is not lower than the set voltage; and a clock signal generating circuit that outputs, based on a reference clock signal, a clock signal and an inverted clock signal obtained by inverting the clock signal, and stops outputs of the clock signal and the inverted clock signal in response to the second detecting signal.
摘要翻译：从输出端子输出设定电压的电源电路具有升压电路，其升压从电源供给的电压，并将该电压输出到输出端子; 电压检测电路，当从升压电路输出的电压不低于设定电压以下的第一检测电压时，输出第一检测信号，并且当从升压电路输出的电压不低时输出第二检测信号比设定电压; 以及时钟信号发生电路，其基于参考时钟信号输出通过反相时钟信号而获得的时钟信号和反相时钟信号，并响应于第二检测信号停止时钟信号和反相时钟信号的输出。

6. 发明申请

US20080290852A1 POWER SUPPLY CIRCUIT AND SEMICONDUCTOR MEMORY 有权
标题翻译：电源电路和半导体存储器
公开(公告)号：US20080290852A1
公开(公告)日：2008-11-27
申请号：US12125589
申请日：2008-05-22
申请人： Mikio Ogawa , Yasuhiro Suematsu
发明人： Mikio Ogawa , Yasuhiro Suematsu
IPC分类号： G05F1/00
CPC分类号： H02M3/073 , G11C5/143 , G11C5/145 , G11C16/30
摘要： A power supply circuit that outputs a set voltage from an output terminal, has a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first detecting signal when the voltage outputted from the boosting circuit is not lower than a first detection voltage set lower than the set voltage, and outputs a second detecting signal when the voltage outputted from the boosting circuit is not lower than the set voltage; and a clock signal generating circuit that outputs, based on a reference clock signal, a clock signal and an inverted clock signal obtained by inverting the clock signal, and stops outputs of the clock signal and the inverted clock signal in response to the second detecting signal.
摘要翻译：从输出端子输出设定电压的电源电路具有升压电路，其升压从电源供给的电压，并将该电压输出到输出端子; 电压检测电路，当从升压电路输出的电压不低于设定电压以下的第一检测电压时，输出第一检测信号，并且当从升压电路输出的电压不低时输出第二检测信号比设定电压; 以及时钟信号发生电路，其基于参考时钟信号输出通过反相时钟信号而获得的时钟信号和反相时钟信号，并响应于第二检测信号停止时钟信号和反相时钟信号的输出。

7. 发明授权

US06519198B2 Semiconductor memory device 失效
公开(公告)号：US06519198B2
公开(公告)日：2003-02-11
申请号：US09935010
申请日：2001-08-21
申请人： Yasuhiro Suematsu , Masaru Koyanagi
发明人： Yasuhiro Suematsu , Masaru Koyanagi
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C11/4074 , G11C11/4094
摘要： The bit line overdrive circuit of the present invention comprises a VBLH potential generation circuit generating a bit line final potential relative to a VBLH power supply line for driving a sense amplifier, a charge adjusting capacitance C, a transistor for supplying an overdrive potential to the VBLH power supply line, and a transistor for connecting a PCS node to the VBLH power supply line. The charge pre-charged from the overdrive potential to the VBLH power supply line is shared among the capacitance of the above-noted circuit elements connected to the VBLH power supply line, the bit line capacitance, and the capacitance of a cell capacitor so as to form a VBLH power supply of a substantially one system, thereby avoiding the generation of a power supply noise caused by the power supply switching.

8. 发明授权

US08861287B2 Interface circuit 有权
标题翻译：接口电路
公开(公告)号：US08861287B2
公开(公告)日：2014-10-14
申请号：US13616609
申请日：2012-09-14
申请人： Yuui Shimizu , Masaru Koyanagi , Yasuhiro Suematsu
发明人： Yuui Shimizu , Masaru Koyanagi , Yasuhiro Suematsu
IPC分类号： G11C7/10 , G11C16/24 , H03K19/003 , H03K19/0175 , G11C16/26
CPC分类号： H03K19/017509 , G11C7/1057 , G11C16/24 , G11C16/26 , H03K19/00361
摘要： According to an embodiment, an interface circuit is provided with an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor and a driver circuit which drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor.
摘要翻译：根据实施例，接口电路设置有输出缓冲器，其基于晶体管的导通/截止操作和驱动晶体管的驱动器电路产生输出波形，并且能够独立地改变导通速度和晶体管的截止速度。

9. 发明授权

US08242812B2 Buffer circuit 有权
标题翻译：缓冲电路
公开(公告)号：US08242812B2
公开(公告)日：2012-08-14
申请号：US12963194
申请日：2010-12-08
申请人： Masaru Koyanagi , Fumiyoshi Matsuoka , Yasuhiro Suematsu
发明人： Masaru Koyanagi , Fumiyoshi Matsuoka , Yasuhiro Suematsu
IPC分类号： H03K3/00
CPC分类号： H03K19/00384
摘要： A buffer circuit in accordance with an embodiment comprises output transistors connected between a first fixed voltage terminal and an output terminal, and gate control transistors connected between a second fixed voltage terminal and a gate of one of the output transistors or between two of gates of the output transistors. The output transistors are configured to turn on to change a voltage of the output terminal. The gate control transistors are configured to apply a gate voltage to the gates of the output transistors. A gate of each of the gate control transistors is applied with a certain voltage, such that when a source of each of the gate control transistors changes from a first potential to a second potential, a potential difference between the gate and the source attains a threshold voltage or greater, whereby each of the gate control transistors is turned on.
摘要翻译：根据实施例的缓冲电路包括连接在第一固定电压端子和输出端子之间的输出晶体管，以及连接在第二固定电压端子和输出晶体管之一的栅极之间或栅极控制晶体管的两个栅极之间的栅极控制晶体管输出晶体管。输出晶体管被配置为导通以改变输出端子的电压。栅极控制晶体管被配置为向输出晶体管的栅极施加栅极电压。每个栅极控制晶体管的栅极被施加一定电压，使得当每个栅极控制晶体管的源极从第一电位变为第二电位时，栅极和源极之间的电位差达到阈值电压或更大，由此每个栅极控制晶体管导通。

10. 发明申请

US20110133792A1 BUFFER CIRCUIT 有权
标题翻译：缓冲电路
公开(公告)号：US20110133792A1
公开(公告)日：2011-06-09
申请号：US12963194
申请日：2010-12-08
申请人： Masaru KOYANAGI , Fumiyoshi Matsuoka , Yasuhiro Suematsu
发明人： Masaru KOYANAGI , Fumiyoshi Matsuoka , Yasuhiro Suematsu
IPC分类号： H03K3/00
CPC分类号： H03K19/00384
摘要： A buffer circuit in accordance with an embodiment comprises output transistors connected between a first fixed voltage terminal and an output terminal, and gate control transistors connected between a second fixed voltage terminal and a gate of one of the output transistors or between two of gates of the output transistors. The output transistors are configured to turn on to change a voltage of the output terminal. The gate control transistors are configured to apply a gate voltage to the gates of the output transistors. A gate of each of the gate control transistors is applied with a certain voltage, such that when a source of each of the gate control transistors changes from a first potential to a second potential, a potential difference between the gate and the source attains a threshold voltage or greater, whereby each of the gate control transistors is turned on.
摘要翻译：根据实施例的缓冲电路包括连接在第一固定电压端子和输出端子之间的输出晶体管，以及连接在第二固定电压端子和输出晶体管之一的栅极之间或栅极控制晶体管的两个栅极之间的栅极控制晶体管输出晶体管。输出晶体管被配置为导通以改变输出端子的电压。栅极控制晶体管被配置为向输出晶体管的栅极施加栅极电压。每个栅极控制晶体管的栅极被施加一定电压，使得当每个栅极控制晶体管的源极从第一电位变为第二电位时，栅极和源极之间的电位差达到阈值电压或更大，由此每个栅极控制晶体管导通。

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