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1. 发明申请

US20130043901A1 ON-DIE TERMINATION CIRCUIT 有权
标题翻译：端子终止电路
公开(公告)号：US20130043901A1
公开(公告)日：2013-02-21
申请号：US13657123
申请日：2012-10-22
申请人： Yong Ju KIM , Hyung Soo KIM , Hae Rang CHOI , Jae Min JANG
发明人： Yong Ju KIM , Hyung Soo KIM , Hae Rang CHOI , Jae Min JANG
IPC分类号： H03K17/16
CPC分类号： H04L25/0298
摘要： An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.
摘要翻译：片上终端电路包括：参考周期信号生成电路，其根据参考电压的电平生成基准周期信号;第一周期信号生成电路，其根据电压的电平生成第一周期信号; 周期比较电路，其将第一周期信号的周期与基准周期信号的周期进行比较，并计数多个驱动信号;以及驱动器电路，其响应于多个驱动信号而驱动该焊盘。

2. 发明申请

US20100034033A1 RECEIVER OF SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器接收器
公开(公告)号：US20100034033A1
公开(公告)日：2010-02-11
申请号：US12483413
申请日：2009-06-12
申请人： Tae Jin HWANG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Hae Rang CHOI , Ji Wang LEE , Jae Min JANG , Chang Kun PARK
发明人： Tae Jin HWANG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Hae Rang CHOI , Ji Wang LEE , Jae Min JANG , Chang Kun PARK
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1084
摘要： A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.
摘要翻译：半导体存储装置的接收器包括：第一输入晶体管，其配置为当输入信号等于或大于预定电平时导通; 配置为当输入信号等于或小于预定电平时导通的第二输入晶体管; 第一输出节点电压控制单元，被配置为当所述第一输入晶体管导通时增加输出节点的电压电平; 第二输出节点电压控制单元，被配置为当所述第二输入晶体管导通时降低所述输出节点的电压电平; 第三输入晶体管，被配置为当所述输入信号的反相信号等于或小于所述预定电压电平时，增加所述输出节点的电压电平; 以及第四输入晶体管，被配置为当输入信号的反相信号等于或大于预定电压电平时降低输出节点的电压电平。

3. 发明申请

US20100117696A1 DLL CIRCUIT, UPDATE CONTROL APPARATUS IN DLL CIRCUIT AND UPDATE METHOD OF DLL CIRCUIT 有权
标题翻译： DLL电路中的DLL电路，更新控制装置和DLL电路的更新方法
公开(公告)号：US20100117696A1
公开(公告)日：2010-05-13
申请号：US12493387
申请日：2009-06-29
申请人： Jae Min JANG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Hae Rang CHOI , Ji Wang LEE , Chang Kun PARK
发明人： Jae Min JANG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Hae Rang CHOI , Ji Wang LEE , Chang Kun PARK
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/085
摘要： A delay locked loop (DLL) circuit includes a phase detection unit configured to generate a phase detection signal by comparing a phase of a reference clock signal with a phase of a feedback clock signal. An update control apparatus is configured to generate a valid interval signal and an update control signal by determining a difference between the number of first logical values and the number of second logical values of the phase detection signal in response to the reference clock signal. A shift register configured to update a delay value granted to a delay line in response to the update control signal when the valid interval signal is enabled.
摘要翻译：延迟锁定环路（DLL）电路包括：相位检测单元，被配置为通过将参考时钟信号的相位与反馈时钟信号的相位进行比较来产生相位检测信号。更新控制装置被配置为通过响应于参考时钟信号确定第一逻辑值的数量和相位检测信号的第二逻辑值的数量之间的差异来产生有效间隔信号和更新控制信号。移位寄存器，被配置为当有效间隔信号被使能时响应于更新控制信号来更新授予延迟线的延迟值。

4. 发明申请

US20100044872A1 SEMICONDUCTOR MEMORY DEVICE HAVING PADS 有权
标题翻译：具有PADS的半导体存储器件
公开(公告)号：US20100044872A1
公开(公告)日：2010-02-25
申请号：US12493617
申请日：2009-06-29
申请人： Chang Kun PARK , Seong Hwi SONG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Hae Rang CHOI , Ji Wang LEE , Jae Min JANG
发明人： Chang Kun PARK , Seong Hwi SONG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Hae Rang CHOI , Ji Wang LEE , Jae Min JANG
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L24/06 , H01L23/5286 , H01L24/09 , H01L27/1052 , H01L2224/061 , H01L2224/0612 , H01L2224/06515 , H01L2224/091 , H01L2224/09515 , H01L2924/14 , H01L2924/1434 , H01L2924/30101 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
摘要翻译：半导体存储器件包括具有芯片焊盘形成区域的半导体电路基板。在芯片焊盘区域一侧的半导体电路基板上形成一对数据线。一对数据线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸。这对数据线被布置为彼此相邻并且接收一对差分数据信号。电源线形成在芯片焊盘区域的另一侧的半导体电路基板上。电源线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸，并且电源线接收电力。

5. 发明申请

US20110241726A1 ON-DIE TERMINATION CIRCUIT 有权
标题翻译：端子终止电路
公开(公告)号：US20110241726A1
公开(公告)日：2011-10-06
申请号：US13012972
申请日：2011-01-25
申请人： Yong Ju KIM , Hyung Soo KIM , Hae Rang CHOI , Jae Min JANG
发明人： Yong Ju KIM , Hyung Soo KIM , Hae Rang CHOI , Jae Min JANG
IPC分类号： H03K19/003
CPC分类号： H04L25/0298
摘要： An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.
摘要翻译：片上终端电路包括：参考周期信号生成电路，其根据参考电压的电平生成基准周期信号;第一周期信号生成电路，其根据电压的电平生成第一周期信号; 周期比较电路，其将第一周期信号的周期与基准周期信号的周期进行比较，并计数多个驱动信号;以及驱动器电路，其响应于多个驱动信号而驱动该焊盘。

6. 发明申请

US20100148833A1 DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器装置的域交叉电路
公开(公告)号：US20100148833A1
公开(公告)日：2010-06-17
申请号：US12486281
申请日：2009-06-17
申请人： Hae Rang CHOI , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Ji Wang LEE , Jae Min JANG , Chang Kun PARK
发明人： Hae Rang CHOI , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Ji Wang LEE , Jae Min JANG , Chang Kun PARK
IPC分类号： H03L7/00
CPC分类号： H04L7/0338 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , H04L7/0045
摘要： The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.
摘要翻译：用于提高定时裕度的半导体存储装置的域交叉电路包括：采样器，其通过响应于时钟和内部输入信号产生的采样内部信号，边缘信息信号定义为输出定时采样内部信号和输出级，其允许采样内部信号与时钟同步，以响应于作为最终输出信号输出的边缘信息信号。

7. 发明申请

US20130235682A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20130235682A1
公开(公告)日：2013-09-12
申请号：US13602140
申请日：2012-09-01
申请人： Hyung Soo KIM
发明人： Hyung Soo KIM
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C11/4094
摘要： A semiconductor apparatus including an equalizing unit configured to equalize voltages of a bit line and a bit bar line in response to an equalization signal; a precharge circuit unit configured to supply a voltage to the bit line and the bit bar line in response to first and second precharge signals; and a control unit configured to receive the equalization signal, and generate the equalization signal as the first and second precharge signals according to a control signal.
摘要翻译：一种半导体装置，包括均衡单元，其被配置为响应于均衡信号来均衡位线和位线的电压; 预充电电路单元，被配置为响应于第一和第二预充电信号向位线和位线提供电压; 以及控制单元，被配置为接收均衡信号，并根据控制信号产生作为第一和第二预充电信号的均衡信号。

8. 发明申请

US20080023962A1 COGENERATION SYSTEM 审中-公开
标题翻译：加工系统
公开(公告)号：US20080023962A1
公开(公告)日：2008-01-31
申请号：US11831019
申请日：2007-07-31
申请人： Nam Joon CHO , Hyung Soo KIM , Bon Chang HWANG
发明人： Nam Joon CHO , Hyung Soo KIM , Bon Chang HWANG
IPC分类号： F02B63/04
CPC分类号： F25B27/02 , B60H1/00421 , F01P7/04 , F01P2001/005 , F02B63/04 , F02G5/04 , F02G2262/00 , Y02A30/274 , Y02E20/14 , Y02P80/15 , Y02T10/166
摘要： Provided is a cogeneration system. The system includes a chassis, a controller cooling unit, and a driver cooling unit. The chassis is provided with a generator, a driving source, a waste heat recovering unit, and a controller. The generator generates power. The driving source drives the generator and generates heat. The waste heat recovering unit recovers a waste heat of the driving source. The controller controls operations of the generator, the driving source, and the waste heat recovering unit. The controller cooling unit introduces air at one side inside the chassis, circulates the introduced air, and cools at least any one of the generator and the controller. The driver cooling unit introduces air at the other side inside the chassis, circulates the introduced air, and cools at least any one of the driving source and the waste heat recovering unit.
摘要翻译：提供一个热电联产系统。该系统包括底盘，控制器冷却单元和驱动器冷却单元。底盘设置有发电机，驱动源，废热回收单元和控制器。发电机发电。驱动源驱动发电机并产生热量。废热回收单元回收驱动源的余热。控制器控制发电机，驱动源和废热回收单元的操作。控制器冷却单元在机箱内的一侧引入空气，循环引入的空气，并冷却至少任一个发电机和控制器。驱动器冷却单元在底盘内的另一侧引入空气，使引入的空气循环，并冷却至少任一个驱动源和废热回收单元。

9. 发明申请

US20110292750A1 BIT LINE SENSE AMPLIFIER CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME 有权
标题翻译：位线检测放大器控制电路和具有相同功能的半导体存储器件
公开(公告)号：US20110292750A1
公开(公告)日：2011-12-01
申请号：US12959590
申请日：2010-12-03
申请人： Hyung Soo KIM , Ki Myung KYUNG , Ic Su OH
发明人： Hyung Soo KIM , Ki Myung KYUNG , Ic Su OH
IPC分类号： G11C7/06
CPC分类号： G11C7/08 , G11C7/065 , G11C11/4091
摘要： A bit line sense amplifier control circuit is configured to drive a bit line sense amplifier according to a first sense amplifier enable signal and a second sense amplifier enable signal, wherein the driving force of the bit line sense amplifier is changed in response to a column selection control signal.
摘要翻译：位线读出放大器控制电路被配置为根据第一读出放大器使能信号和第二读出放大器使能信号来驱动位线读出放大器，其中位线读出放大器的驱动力响应列选择而改变控制信号。

10. 发明申请

US20090175656A1 IMAGE FORMING APPARATUS 有权
标题翻译：图像形成装置
公开(公告)号：US20090175656A1
公开(公告)日：2009-07-09
申请号：US12252856
申请日：2008-10-16
申请人： Hyung Soo KIM , Sun Min Kin
发明人： Hyung Soo KIM , Sun Min Kin
IPC分类号： G03G15/04
CPC分类号： G03G15/326 , B41J2/473 , G03G15/0435 , H04N1/00525
摘要： An image forming apparatus having improved arrangement of photosensitive members and configuration of a light scanning device to enable size reduction is described. The image forming apparatus includes a plurality of photosensitive members, a light scanning device to irradiate light beams to the plurality of photosensitive members, so as to form electrostatic latent images on the photosensitive members, a plurality of developers to supply a developing agent to the photosensitive members, so as to form visible images on the photosensitive members, and a transfer drum disposed in contact with the photosensitive members and used to transfer the visible images such that the visible images overlap one another. Scanning lines, which are formed on the plurality of photosensitive members, respectively, by the light scanning device, are arranged in at least two different planes.
摘要翻译：描述了一种具有改进的感光构件布置的图像形成装置和光扫描装置的配置以使尺寸减小。图像形成装置包括多个感光构件，用于将光束照射到多个感光构件的光扫描装置，以便在感光构件上形成静电潜像，多个显影剂将显影剂供应到感光体以便在感光构件上形成可见图像，以及与感光构件接触设置的转印鼓，用于传送可见图像使得可视图像彼此重叠。分别由光扫描装置形成在多个感光构件上的扫描线被布置在至少两个不同的平面中。

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