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1. 发明申请

US20100148833A1 DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器装置的域交叉电路
公开(公告)号：US20100148833A1
公开(公告)日：2010-06-17
申请号：US12486281
申请日：2009-06-17
申请人： Hae Rang CHOI , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Ji Wang LEE , Jae Min JANG , Chang Kun PARK
发明人： Hae Rang CHOI , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Ji Wang LEE , Jae Min JANG , Chang Kun PARK
IPC分类号： H03L7/00
CPC分类号： H04L7/0338 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , H04L7/0045
摘要： The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.
摘要翻译：用于提高定时裕度的半导体存储装置的域交叉电路包括：采样器，其通过响应于时钟和内部输入信号产生的采样内部信号，边缘信息信号定义为输出定时采样内部信号和输出级，其允许采样内部信号与时钟同步，以响应于作为最终输出信号输出的边缘信息信号。

2. 发明申请

US20100117696A1 DLL CIRCUIT, UPDATE CONTROL APPARATUS IN DLL CIRCUIT AND UPDATE METHOD OF DLL CIRCUIT 有权
标题翻译： DLL电路中的DLL电路，更新控制装置和DLL电路的更新方法
公开(公告)号：US20100117696A1
公开(公告)日：2010-05-13
申请号：US12493387
申请日：2009-06-29
申请人： Jae Min JANG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Hae Rang CHOI , Ji Wang LEE , Chang Kun PARK
发明人： Jae Min JANG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Hae Rang CHOI , Ji Wang LEE , Chang Kun PARK
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/085
摘要： A delay locked loop (DLL) circuit includes a phase detection unit configured to generate a phase detection signal by comparing a phase of a reference clock signal with a phase of a feedback clock signal. An update control apparatus is configured to generate a valid interval signal and an update control signal by determining a difference between the number of first logical values and the number of second logical values of the phase detection signal in response to the reference clock signal. A shift register configured to update a delay value granted to a delay line in response to the update control signal when the valid interval signal is enabled.
摘要翻译：延迟锁定环路（DLL）电路包括：相位检测单元，被配置为通过将参考时钟信号的相位与反馈时钟信号的相位进行比较来产生相位检测信号。更新控制装置被配置为通过响应于参考时钟信号确定第一逻辑值的数量和相位检测信号的第二逻辑值的数量之间的差异来产生有效间隔信号和更新控制信号。移位寄存器，被配置为当有效间隔信号被使能时响应于更新控制信号来更新授予延迟线的延迟值。

3. 发明申请

US20100044872A1 SEMICONDUCTOR MEMORY DEVICE HAVING PADS 有权
标题翻译：具有PADS的半导体存储器件
公开(公告)号：US20100044872A1
公开(公告)日：2010-02-25
申请号：US12493617
申请日：2009-06-29
申请人： Chang Kun PARK , Seong Hwi SONG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Hae Rang CHOI , Ji Wang LEE , Jae Min JANG
发明人： Chang Kun PARK , Seong Hwi SONG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Tae Jin HWANG , Hae Rang CHOI , Ji Wang LEE , Jae Min JANG
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L24/06 , H01L23/5286 , H01L24/09 , H01L27/1052 , H01L2224/061 , H01L2224/0612 , H01L2224/06515 , H01L2224/091 , H01L2224/09515 , H01L2924/14 , H01L2924/1434 , H01L2924/30101 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
摘要翻译：半导体存储器件包括具有芯片焊盘形成区域的半导体电路基板。在芯片焊盘区域一侧的半导体电路基板上形成一对数据线。一对数据线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸。这对数据线被布置为彼此相邻并且接收一对差分数据信号。电源线形成在芯片焊盘区域的另一侧的半导体电路基板上。电源线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸，并且电源线接收电力。

4. 发明申请

US20100034033A1 RECEIVER OF SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器接收器
公开(公告)号：US20100034033A1
公开(公告)日：2010-02-11
申请号：US12483413
申请日：2009-06-12
申请人： Tae Jin HWANG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Hae Rang CHOI , Ji Wang LEE , Jae Min JANG , Chang Kun PARK
发明人： Tae Jin HWANG , Yong Ju KIM , Sung Woo HAN , Hee Woong SONG , Ic Su OH , Hyung Soo KIM , Hae Rang CHOI , Ji Wang LEE , Jae Min JANG , Chang Kun PARK
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1084
摘要： A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.
摘要翻译：半导体存储装置的接收器包括：第一输入晶体管，其配置为当输入信号等于或大于预定电平时导通; 配置为当输入信号等于或小于预定电平时导通的第二输入晶体管; 第一输出节点电压控制单元，被配置为当所述第一输入晶体管导通时增加输出节点的电压电平; 第二输出节点电压控制单元，被配置为当所述第二输入晶体管导通时降低所述输出节点的电压电平; 第三输入晶体管，被配置为当所述输入信号的反相信号等于或小于所述预定电压电平时，增加所述输出节点的电压电平; 以及第四输入晶体管，被配置为当输入信号的反相信号等于或大于预定电压电平时降低输出节点的电压电平。

5. 发明申请

US20110029700A1 SEMICONDUCTOR APPARATUS 失效
公开(公告)号：US20110029700A1
公开(公告)日：2011-02-03
申请号：US12648524
申请日：2009-12-29
申请人： Ji Wang LEE , Hee Woong SONG , Tae Jin HWANG
发明人： Ji Wang LEE , Hee Woong SONG , Tae Jin HWANG
IPC分类号： G06F1/12
CPC分类号： G06F13/4072
摘要： A semiconductor apparatus includes a clock input buffer, an asynchronous data input buffer, and a synchronous data input buffer. The clock input buffer is configured to buffer an external clocks in order to generate an internal clock. The asynchronous data input buffer is configured to buffer data input through a data pad and output the buffered data. The synchronous data input buffer is configured to be synchronous with the internal clock to buffer the buffered data. The semiconductor apparatus is arranged so that the length of a line for transferring the internal clock to the synchronous data input buffer and the length of a line for transferring the buffered data to the synchronous data input buffer are substantially equal to each other.
摘要翻译：半导体装置包括时钟输入缓冲器，异步数据输入缓冲器和同步数据输入缓冲器。时钟输入缓冲器配置为缓冲外部时钟以产生内部时钟。异步数据输入缓冲器被配置为缓冲通过数据焊盘输入的数据并输出缓冲的数据。同步数据输入缓冲器被配置为与内部时钟同步以缓冲缓冲的数据。半导体装置被布置成使得用于将内部时钟传送到同步数据输入缓冲器的线的长度和用于将缓冲数据传送到同步数据输入缓冲器的线的长度基本上彼此相等。

6. 发明申请

US20140286082A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20140286082A1
公开(公告)日：2014-09-25
申请号：US14018306
申请日：2013-09-04
申请人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
发明人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
摘要翻译：根据一个实施例，存储器件包括存储单元，读出放大器和电阻器。读出放大器包括第一输入和第二输入，根据第一和第二输入之间的差输出信号，并且在第二输入端选择性地耦合到存储单元。电阻器位于读出放大器的第一输入端和接地节点之间的第一路径中。

7. 发明申请

US20140286088A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20140286088A1
公开(公告)日：2014-09-25
申请号：US14018148
申请日：2013-09-04
申请人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
发明人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1659
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.
摘要翻译：根据一个实施例，存储器件包括存储器单元，读出放大器，单元结构和参考信号发生器。每个结构包括第一端，第一晶体管，第一局部线，可变电阻元件，第二晶体管，第二本地线和串联耦合的第三晶体管。参考信号发生器包括第一至第四全局线，以及第一和第二单元结构。第一单元结构在第一端耦合到第一全局线并且在第二端耦合到第三全局线。第二单元结构在第一端耦合到第四全局线并且在第二端耦合到第二全局线。

8. 发明申请

US20160019955A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20160019955A1
公开(公告)日：2016-01-21
申请号：US14872908
申请日：2015-10-01
申请人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
发明人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
摘要翻译：根据一个实施例，存储器件包括存储单元，读出放大器和电阻器。读出放大器包括第一输入和第二输入，根据第一和第二输入之间的差输出信号，并且在第二输入端选择性地耦合到存储单元。电阻器位于读出放大器的第一输入端和接地节点之间的第一路径中。

9. 发明申请

US20140286075A1 RESISTANCE CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20140286075A1
公开(公告)日：2014-09-25
申请号：US14018287
申请日：2013-09-04
申请人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
发明人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
IPC分类号： G11C13/00 , G11C5/08 , G11C5/06
CPC分类号： G11C13/004 , G11C5/06 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2013/0054
摘要： According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.
摘要翻译：根据一个实施例，存储器包括存储单元阵列，其包括沿列方向布置的块，第一和第二主全局导线，每列从列方向上从存储单元阵列的第一端延伸到第二端，第一电阻连接在存储单元阵列内部的第一和第二主要全局导电线之间的改变元件，从列方向上从存储单元阵列的第一端延伸到第二端的第一参考全局导电线，以及连接到存储单元阵列的第二电阻变化元件到存储单元阵列外的参考全局导线。

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